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| ST7272 8-BIT MCU WITH 24K ROM, EEPROM, ADC, PWM/BRM DACs, SYNC PROCESSOR, EWPCC, TIMER AND DDC INTERFACE PRELIMINARY DATA s s s s s s s s s s 4.5V to 5.5V Supply Operating Range 8MHz Maximum Oscillator Frequency Fully Static operation 0C to + 70C Operating Temperature Range Run, Wait, and Halt modes User ROM: 24Kbytes Data RAM: 384 bytes EEPROM: 640 + 256 bytes 56 pin Shrink Dual-in-Line plastic package 27 multifunctional bidirectional I/O lines: - 8 lines with 12V open-drain drive capability - 8 Programmable Interrupt inputs - 8 Analog inputs s 16-bit Timer, featuring: - 2 Input Captures - 2 Output Compares (1 output pin) PSDIP56 (See end of Datasheet for Ordering Information) s s s s s s 8-bit Analog-to-Digital converter Programmable Watchdog Timer 16 10-bit PWM/BRM Digital to Analog outputs 2 12-bit PWM/BRM Digital to Analog outputs EWPCC circuit with on-chip EEPROM New upgraded Sync processor for Mode Recognition, Power Management and Composite Video Blanking generation DDC 1/2/AB interface with built-in DMA and 2C I Master/Slave Modes Master Reset and Power-On Reset 8-bit Data Manipulation 63 Basic Instructions 17 main Addressing Modes 8 x 8 Unsigned Multiply Instruction True Bit Manipulation Complete Development Support on PC/DOS Real-Time Emulator Full Software Package (C-Compiler, CrossAssembler, Debugger) s s s s s s s s s May 1996 This is advance information from SGS-TH OMSON. Details are subject tochange without notice. 1/119 1 Table of Contents ST7272 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 3.1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 3.1.2 Crystal Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 3.1.3 Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.1.4 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.2 MISCELLANEOUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.3.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.3.3 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 3.4 WATCHDOG TIMER SYSTEM (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 3.4.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.3 Watchdog Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3.5.2 Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3.5.3 Port B Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3.5.4 RX interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3.5.5 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 3.6 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.6.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.6.3 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2/119 2 Table of Contents 4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 4.1 EEPROM (EEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 4.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 4.1.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1.2.1Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1.2.2Write/Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1.3 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 4.1.4 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 4.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 4.2.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.2.2.1Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 4.2.2.2Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 4.2.2.3Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 4.2.2.4Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 4.2.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 4.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 4.3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3.3 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 4.3.4 Input Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 4.3.5 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 4.3.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.4 SYNC PROCESSOR (SYNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.4.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.4.3.1Checking the presence of input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.4.3.2Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.4.3.3VSYNCO Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.4.3.4Standard Discrimination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.4.3.5Video Blanking Signal Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.4.3.6Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 4.4.3.7Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 4.4.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 3/119 3 Table of Contents 4.5 DIGITAL TO ANALOG CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 . 4.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 . 4.5.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 . 4.5.2.110-bit PWM/BRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 . 4.5.2.212-Bit PWM/BRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 . 4.5.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 . 4.5.3.110-bit PWM/BRM REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 4.6 EAST-WEST PIN CUSHION CORRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 4.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 . 4.6.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 . 4.6.2.1EWPCC Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 . 4.6.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 . 4.7 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 . 4.7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 . 4.7.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 . 4.7.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 . 4.8 DDC BUS INTERFACE (DDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 . 4.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 . 4.8.1.1DDC Features: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 . 4.8.1.2I2C Features: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 . 4.8.1.3I2C Master Features: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 . 4.8.1.4I2C Slave Features: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 . 4.8.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 . 4.8.2.1DDC1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 . 4.8.2.2DDC2B mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 . 4.8.2.3I2C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 . 4.8.3 4.8.4 4.8.5 4.8.6 4.8.7 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 . DDC1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 . I2C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 . I2C State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 . Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 . 4.8.7.1Slave Sending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 . 4.8.7.2Slave Receiving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 . 4.8.8 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 . 4.8.8.1Master Sending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 . 4.8.8.2Master Receiving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 . 4.8.9 Transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 . 4/119 4 Table of Contents 4.9 DDC DMA CHANNEL (DDC-DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 4.9.2 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 4.9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.9.4 DMA Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.9.5 DDC DMA Channel (DDC-DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5 SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 5.1 ST7 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 5.2 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.3 ST7 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.2 POWER CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.5 CONTROL TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 6.5.1 DDC (I2C BUS) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.5.1.1Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 7 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 7.2.2 Communication of the User ROM Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.2.3 Verification and Formal Approval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 ST72E72 / ST72T72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 1.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 1.4 EPROM ERASURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 2 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 2.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 2.2 POWER CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 2.3 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 2.4 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 2.5 CONTROL TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 2.5.1 DDC (I2C BUS) INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 2.5.1.1Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 3 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 3.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 3.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5/119 5 ST7272 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST7272 HCMOS Microcontroller Unit is a member of the ST7 family of Microcontrollers. The device is based on an industry-standard 8-bit core and features an enhanced instruction set. Oscillator frequency can be as high as 8MHz, however, thanks to the fully static design, operation is possible down to DC. Under software control, the ST7272 may be placed in either WAIT or HALT modes, thus reducing power consumption. The enhanced instruction set and addressing modes afford real programming potential. In addition to standard 8-bit data management, the ST7272 features true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. Figure 1. ST7272 Block Diagram 24 KBytes (1) ROM PORT A PA0-PA7 The device features an on-chip oscillator, CPU, ROM, RAM, EEPROM, 27 multifunctional I/O lines, 12 of which with 12V open-drain drive capability, and the following on-chip peripherals: Analog-to-Digital converter with 8 multiplexed analog inputs, sixteen 10-bit and two 12-bit PWM/BRM analog outputs, EWPCC circuit with EEPROM and analog output, DDC 1/2AB interface with 2C funcI tionality and built-in DMA, digital Watchdog Timer, 16-bit multipurpose Timer featuring 2 Input Captures and 2 Output Compares, and an upgraded Sync Processor offering Mode Recognition, Power Management and Composite Video Blanking generation. EWPCC EEPROM 256 Bytes EWPCC VFBACK PORT B ADC V DDA V SSA EWPCC PB0-PB7 AIN0-AIN7 WAKE-UP INTERRUPT VFBACK (PB0) Ain0-Ain7 RAM 384 Bytes ADDRESS / DATA BUSES DDC (12C) MISO MOSI EEPROM 640 Bytes PORT C CMP0 TIMER H/CSYNC HSYNCI2 PC0-PC5 (PC5) (PC4) SDA1/TX (PC3) SCL1/RX (PC2) HSYNCI2 (PC1) OCMP/HFBAC (PC0) K RESET WATCHDOG CONTROL 8-BIT CORE ALU SYNC PROCESSOR VSYNC SCK SS HSYNCI1 VSYNCI1 PD0-PD4 CSYNCI (PD0) HSYNCO (PD1) VSYNCO (PD2) CLMPO (PD3) VSYNCI2 (PD4) DA0,DA1 12-Bit D/A DA2,DA17 10-Bit D/A PCL PCH SP X Y A CC VSYNCI2 CSYNCI HSYNCO VSYNCO POWER SUPPLY OSC. INTERNAL CLOCK PORT D PWM/BRM VDD V SS OSCin OSCout CLMPO VR02069A Note1: EPROM/OTP versions also available 6/119 6 ST7272 1.2 PIN DESCRIPTION VDD Power supply VSS Digital Ground VDDA Analog VDD and reference for EWPCC Digital to Analog Converter (typically 8 Volts). VSSA Analog VSS for EWPCC DAC. OSCin, OSCout Oscillator input and output pins; usually connected to a parallel resonant crystal or ceramic resonator. Altenatively an external clock source may also be input via OSCin. EWPCC Analog correction signal output from East-West Pin Cushion Correction circuit. SCL1/RX DDC Serial Clock or RX (Falling edge detector with interrupt). SDA1/TX DDC Serial Data or TX. OCMP / HFBACK Output compare signal from the Timer. HSYNCI1 Horizontal Synchronization Input 1. VSYNCI1 Vertical Synchronization Input 1. HSYNCI2 Sync Processor Horizontal or complete Synchronization Input 2. VSYNCI2 Vertical Synchronization Input 2. CSYNCI Composite Synchronization Input. This pin accepts the composite synchronization input when the Sync Processor I/O functions are enabled. VFBACK Vertical Flyback signal used for timing correlation for the East-West Pin Cushion correction. HFBACK Horizontal Flyback Input. BLANK OUT Video Blanking Output. HSYNCO Horizontal Synchronization Output from the Sync Processor. VSYNCO Vertical Synchronization Output from the Sync Processor. CLMPO Clamp Output. This pin outputs the clamping (back porch) output signal from the Sync Processor . DA0, DA1 12-bit PWM/BRM outputs (for Analog Controls, after external filtering). DA2-DA17 10-bit PWM/BRM outputs (for Analog controls, after external filtering). PORT A 8 I/O lines, bit programmable, accessed through PADDR and PADR Registers. Each bit 7/119 can be defined as a standard input port bit without pull-up resistor or as an open drain output port (up to 12V). PORT B 8 Standard bit-programmable I/O lines accessed through the PBDDR and PBDR Registers. Each bit can be programmed as an analog input (by control bits in the PORT B Configuration register), digital input (with internal pull-up resistor), push-pull digital output or as interrupt wakeup (with pull-up). These negative edge or low-level sensitive interrupt lines can wake-up the MCU from WAIT or HALT mode. PB0 is used for the East-West Pin cushion controller VFBACK input when the EWPCC is used. PORT C 6 Standard bit-programmable I/O lines accessed through the PCDDR and PCDR Registers. PC 0,1 are Inputs with Pull-Up or Push-Pull Outputs, PC 2,3 are Open Drain outputs or Inputs without Pull-Up, PC 4,5 are Open Drain outputs or Digital Inputs with or without Pull-Up internal resistor. The pull-up resistor is enabled for all bits by one control bit in the Programmable Input/Output Configuration Register. PC0 can also be configured as Timer Output Compare pin or Horizontal Flyback Input. PC1 can be programmed as HSYNCI2 sync input for the Sync Processor. PC2/SCL1 and PC3/SDA1 are alternate functions with the DDC cell. PORT D 5 Standard bit-programmable I/O lines accessed through PDDDR and PDDR Registers. Each bit can be programmed as an input (with internal pull-up resistor), push-pull output or Synchronization inputs and outputs to/from the Sync Processor. When programmed as inputs, Video Synchronization signals can be directly inspected. The inputs may also be passed through the Sync Processor to the Timer Input Captures. RESET An active-low signal on this pin forces initialization of the MCU. This is the top priority non maskable interrupt. This pin is driven low if the Watchdog Timer has been triggered. The resulting pulse can be used to reset external peripherals. TEST This pin must be held low for normal operation. CAUTION: The TEST pin MUST be connected directly to the VSS pin on the device in order to ensure correct operation. 7 ST7272 PIN DESCRIPTION (Cont'd) The following table describes basic and alternate functions for each pin. Relevant ancillary information is given in the Remarks column. The pin configuration is illustrated for convenience. ST7272 Pin Configuration 1 2 3 56 55 54 26 27 28 31 30 29 VR01740A Pin Name(s) V DDA EWPCC DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 / VFBACK PD4 / VSYNCI2 PD3 / CLMPO DA10 DA11 Basic Function Analog power supply EWPCC circuit analog output 12-bit DAC PWM outputs Alternate Function -- Pin 1 2 3 4 5 6 7 Typically +8V 2 - 6V Remarks 10-bit DAC PWM outputs -- 8 9 10 11 12 13 14 15 Generated by PWM/BRM circuitry, need external filtering. Analog input Port B I/Os 16 17 18 19 Standard I/O or alternate function. The I/O configuration is software programmable as input with pull-ups, wake-up interrupt input, or pushpull output. Analog input or VFBACK Port D I/O Port D I/O 10-bit DAC PWM outputs VSYNCI2 CLMPO - 20 As above, or input for EWPCC circuit, when active. Vertical Sync input 2 (TTL with pull-up). Clamp output from Sync circuit. Generated by PWM/BRM circuitry, need external filtering. 21 22 23 24 8/119 8 ST7272 PIN DESCRIPTION (Cont'd) The following table describes basic and alternate functions for each pin. Relevant ancillary information is given in the Remarks column. The pin configuration is illustrated for convenience. ST7272 Pin Configuration 1 2 3 56 55 54 26 27 28 31 30 29 VR01740A Pin Name(s) Basic Function General reset input and output Alternate Function Pin Remarks As an input, a Reset is generated by an active low signal; when the Watchdog has triggered this pin will be driven low to reset external peripherals. Vertical Sync output from Sync processor. Vertical Sync input to Sync processor (TTL with pull-up). 4.5 - 5.5V Horizontal Sync input to Sync processor (TTL with pull-up). Horizontal Sync output from Sync processor. Composite Sync input (TTL with pull-up). These pins may be connected to a parallel resonant crystal or ceramic resonator; alternatively an external clock source may be connected to OSCIN. Generated by PWM/BRM circuitry, need external filtering. Video blanking output from Sync processor. RESET - 25 PD2 / VSYNCO VSYNCI1 V DD HSYNCI1 PD1 / HSYNCO PD0 / CSYNCI OSCOUT OSCIN DA12 DA13 PA7 / BLANKOUT PA6 PA5 PA4 PA3 PA2 PA1 PA0 Port D I/O VSYNCI1 Power supply to digital circuits. HSYNCI1 VSYNCO 26 27 - 28 29 HSYNCO Port D I/Os CSYNCI Oscillator output Oscillator input 10-bit DAC PWM outputs - 30 31 32 33 34 35 36 37 38 BLANKOUT Port A I/Os - 39 40 41 42 43 Standard I/Os, bit programmable via PADDR and PADR registers as inputs without pull-ups or as open-drain outputs (up to 12V). 9/119 9 ST7272 PIN DESCRIPTION (Cont'd) The following table describes basic and alternate functions for each pin. Relevant ancillary information is given in the Remarks column. The pin configuration is illustrated for convenience. ST7272 Pin Configuration 1 2 3 56 55 54 26 27 28 31 30 29 VR01740A Pin Name(s) DA14 DA15 DA16 DA17 TEST PC0 / OCMP / HFBACK PC1 / HSYNCI2 PC2 / SCL1 / RX PC3 / SDA1 / TX PC4 PC5 V SS V SSA Basic Function 10-bit DAC PWM outputs Alternate Function Pin 44 45 46 47 Remarks Generated by PWM/BRM circuitry, need external filtering. This pin is for SGS-THOMSON internal use only and MUST be tied directly to VSS for normal operation Output compare from Timer peripheral. or Horizontal flyback input (TTL with pull-up). Horizontal Sync input to Sync processor (TTL with pull-up). DDC serial clock. Can generate interrupt on falling edge for RX Start detection for software SCI. DDC serial data. OCMP can generate interrupt for TX bit timing for software SCI. - TEST OCMP or HFBACK HSYNCI2 SCL1 48 49 50 Port C I/Os RX 51 SDA1 TX Digital Ground Analog Ground - 52 53 54 55 56 10/119 10 ST7272 1.3 MEMORY MAP Table 1. ST7272 Memory Map Add 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h PWM/B RM TIM EEP EW DACR PCC0 PCC1 CR0 CR1 CR2 CR3 CR SR IC1HR IC1LR OC1HR OC1LR CNTHR CNTLR ACNTHR ACNTLR IC2HR IC2LR OC2HR OC2LR PWM0 BRM0 PWM1 BRM1 ADC Block name Block Register mnemonic PADR PBDR PCDR PDDR PADDR PBDDR PCDDR PDDDR DR CR Register name Port A Data Register Port B Data Register Port C Data Register Port D Data Register Port A Data Direction Register Port B Data Direction Register Port C Data Direction Register Port D Data Direction Register ADC Data Register ADC control/Status register Reserved East/West DAC Register East/West Control 0 East/West Control 1 DDC EEPROM Control register GP1 EEPROM Control register GP2 EEPROM Control register E/W EEPROM Control register TIMER Control Register TIMER Status Register TIMER Input Capture High Register 1 TIMER Input Capture Low Register 1 TIMER Output Compare High Register 1 TIMER Output Compare Low Register 1 TIMER Counter High Register TIMER Counter Low Register TIMER Alternate Counter High Register TIMER Alternate Counter Low Register TIMER Input Capture High Register 2 TIMER Input Capture Low Register 2 TIMER Output Compare High Register 2 TIMER Output Compare Low Register 2 (12-BIT PWM) Register (12-BIT BRM) Register (12-BIT PWM) Register (12-BIT BRM) Register 00h 00h C0h 00h 00h 00h 00h 00h & 02h XXh XXh XXh XXh XXh FFh FCh FFh FCh XXh XXh XXh XXh 80h C0h 80h C0h R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register Read Only Register Read only Read only R/W Register R/W Register Read only R/W Register Read only R/W Register Read only Read only R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register Reset Status XXh XXh XXh XXh 00h 00h 00h 00h XX 00h Remarks R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register Read Only Register R/W Register 11/119 11 ST7272 Add 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h Block name Block Register mnemonic PWM2 BRM3 + BRM2 PWM3 PWM4 BRM5+ BRM4 PWM5 PWM6 BRM7 + BRM6 PWM7 PWM8 BRM9+ BRM8 Register name Reset Status 80h 00h 80h 80h 00h 80h 80h 00h 80h 80h 00h 80h 80h 00h 80h 80h 00h 80h 80h 00h 80h 80h 00h 80h Remarks PWM/B RM PWM9 PWM10 BRM11 + BRM10 PWM11 PWM12 BRM13+ BRM12 PWM13 PWM14 BRM15 + BRM14 PWM15 PWM16 BRM17+ BRM16 PWM17 PBICFGR PIOCFGR WDOGR MISCR CFGR MCR CCR POLR LATR HGENR VGENR ENR 10-BIT PWM/BRM Registers R/W Registers Port B Input Pull-Up Configuration Register Programmable I/O Configuration Register Watchdog Register Miscellaneous Register SYNCHRO Configuration Register SYNCHRO Multiplexer Register SYNCHRO Counter Register SYNCHRO Polarity Register SYNCHRO Latch Register SYNCHRO H Sync Generator Register SYNCHRO V Sync Generator Register SYNCHRO Processor Enable Register 00h F8h 7Fh 2Ah 00h 00h 00h 00h 00h 00h 00h 00h R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register SYNC 12/119 12 ST7272 Add 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059to 005Ah to 007Fh 0080h to 01BFh 01C0h to 01FFh 0200h to 027Fh 0280h to 02FFh 0300h to 03FFh 0400h to 04FFh 0500h to 05FFh Block name Block Register mnemonic IADHR IADLR CADHR Register name DMA Initial High Address Register DMA Initial Low Address Register DMA current High Address Register DMA current Low Address Register DMA Initial Counter Register DMA current Counter Register DMA Control Register Reserved DDC Control Register DDC 1st Status Register DDC 2nd Status Register DDC Clock Control Register DDC 7 Bits Slave address Register Reserved DDC Data Register Reserved CRC Low register / Reserved CRC High register/ Reserved Reserved Reset Status XXh XXh XXh XXh XXh XXh 00h Remarks R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register Read only Read only R/W Register R/W Register R/W Register DMA CADLR ICTR CCTR CTLR CR SR1 SR2 CCR OAR1 DR CRCL CRCH 00h 00h 00h 00h 00h 00h DDC CRC ST INTERNAL USE ONLY User RAM 384 bytes, including stack Stack 64bytes Reserved DDC-EEPROM 128 bytes dedicated for DDC EEPROM GP1-EEPROM 256 bytes for Data GP1 EEPROM EEPROM 896 bytes in 4 banks GP2-EEPROM 256 bytes for Data GP2 EEPROM EWPCC-EEPROM 256 bytes for either EWPCC or Data GP3 EEPROM 13/119 13 ST7272 Add 0600h to 07FFh 0800h to 08FFh 0900h to 13FFh 1400h to 1FFFh 2000h to 7EFFh 7F00h to 7FEFh Block name Block Register mnemonic Register name Reset Status Remarks Unused Reserved Unused Reserved 24K bytes ROM Reserved 7FF0-7FF1 7FF2-7FF3 DDC/DMA (OR wiring) TIMER Overflow TOF TIMER Output compare OCMP TIMER Input capture ICAP RX falling edge Key Board (PORT B) TRAP (software) RESET vector Internal Interrupts " " " " External Interrupts " CPU Interrupt 7FF0h to 7FFFh 7FF4-7FF5 7FF6-7FF7 7FF8-7FF9 7FFA-7FFB 7FFC-7FFD 7FFE-7FFF7 14/119 14 ST7272 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION The CPU has a full 8-bit architecture. Six internal registers allow efficient 8-bit data manipulations. The CPU is capable of executing 63 basic instructions and features 17 main addressing modes. The ST7272 device can address 24 Kbytes of program memory, as well as 384 bytes of data and register memory. 2.2 CPU REGISTERS The 6 CPU registers are shown in the programming model in Figure 2. Following an interrupt, all registers except Y are pushed onto the stack in the order shown in Figure 3. They are popped from stack in the reverse order. The Y register is not affected by these automatic procedures. The interrupt routine must therefore Figure 2. Organisation of Internal CPU Registers 7 ACCUMULATOR: RESET VALUES: XXXXXXXX 7 X INDEX REGISTER: RESET VALUES: XXXXXXXX 7 Y INDEX REGISTER: RESET VALUES: XXXXXXXX PROGRAM COUNTER: 15 0 7 0 0 0 0 handle Y, if necessary, through the PUSH and POP instructions. Accumulator (A). The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations as well as data manipulations. Index Registers (X and Y). These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. The Cross-Assembler generates a PRECEDE instruction (PRE) to indicate that the following instruction refers to the Y register. The Y register is never automatically stacked. Interrupt routines must push or pop it by using the PUSH and POP instructions. Program Counter (PC). The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. RESET VALUE = RESET VECTOR @ 7FFEh-7FFFh 15 0000 7 000111 0 STACK POINTER: RESET VALUES: 0 0 00 0 0 0 1 1 1 1 1 1 1 1 1 CONDITION CODE REGISTER: X = Undefined 76543 111HI 210 NZC RESET VALUES: 111X1010 VR01767E 15/119 15 ST7272 CPU REGISTERS (Cont'd) Stack Pointer (SP) The Stack Pointer is a 16-bit register. Since the stack is 64 bytes deep, the 10 most significant bits are forced as indicated inFigure 2 in order to address the stack as it is mapped in memory. The stack is used to save the CPU context during subroutine calls or interrupts. The user may also directly manipulate the stack by means of the PUSH and POP instructions. Following an MCU Reset, or after a Restore following a Reset Stack Pointer instruction (RSP), the Stack Pointer is set to point to the highest location in the stack. It is then decremented after data has been pushed onto the stack and incremented after data is popped from the stack. When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit. The previously stored information is then overwritten and therefore lost. The upper and lower limits of the stack area are shown in the Memory Map, seeTable 1. A subroutine call occupies two locations and an interrupt five locations in the stack area. Condition Code Register (CC) The Condition Code register is a 5-bit register which indicates the result of the instruction just executed as well as the state of the processor. These bits can be individually tested by a program and specified action taken Figure 3. Stacking Order as a result of their state. The following paragraphs describe each bit of the CC register in turn. Half carry bit (H) The H bit is set to 1 when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. The H bit is useful in BCD arithmetic subroutines. Interrupt mask (I) When the I bit is set to 1, all interrupts except the TRAP software interrupt are disabled. Clearing this bit enables interrupts to be passed to the processor core. Interrupts requested while I is set are latched and can be processed when I is cleared (only one interrupt request per interrupt enable flag can be latched). Negative (N) When set to 1, this bit indicates that the result of the last arithmetic, logical or data manipulation is negative (i.e. the most significant bit is a logic 1). Zero (Z) When set to 1, this bit indicates that the result of the last arithmetic, logical or data manipulation is zero. Carry/Borrow (C) When set, C indicates that a carry or borrow out of the ALU occured during the last arithmetic operation. This bit is also affected during execution of bit test, branch, shift, rotate and store instructions. 7 1 RETURN INCREASING MEMORY ADDRESSES 1 1 CONDITION CODE 0 STACK (PUSH) DECREASING MEMORY ADDRESSES ACCUMULATOR X INDEX REGISTER PCH UNSTACK (POP) PCL VR000074 16/119 16 INTERRUPT ST7272 3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES 3.1 CLOCK SYSTEM 3.1.1 General Description The MCU accepts either a Crystal or Ceramic resonator, or an external clock signal to drive the internal oscillator. The internal clock (CPU CLK running at fCPU) is derived from the external oscillator frequency (fOSC). The external Oscillator clock is first divided by 2, and an additional division factor of 2, 4, 8, or 16 can be applied, in Slow Mode, to reduce the frequency of the CPU clock; this clock signal is also routed to the on-chip peripherals. The CPU clock signal consists of a square wave with a duty cycle of 50%. On Reset, Slow Mode with a division factor of 4 is selected. 3.1.2 Crystal Resonator The internal oscillator is designed to operate with an AT-cut parallel resonant quartz crystal resonator in the frequency range specified for osc. The f circuit shown in Figure 6 is recommended when using a crystal, and Table 2 lists the recommended capacitance and feedback resistance values. The crystal and associated components should be mounted as close as possible to the input pins in order to minimize output distortion and start-up stabilisation time. Use of an external CMOS oscillator is recommended when crystals outside the specified frequency ranges are to be used. Figure 4. External Clock Source Connections Figure 6. Crystal/Ceramic Resonator OSCin OSCin OSCout NC EXTER NAL CLOCK RP OSCout COSCin C OSCout Figure 5. Clock Prescaler Block Diagram. Figure 7. Equivalent Crystal Circuit RS OSCin C1 L1 OSCin OSCout OSCout RP %2 %2,4,8,16 CPUCLK to CPU and Peripherals C0 COSCin COSCout 17/119 17 ST7272 CLOCK SYSTEM (Cont'd) 3.1.3 Ceramic Resonator A ceramic resonator may be used as an alternative to a crystal in low-cost applications. The circuit shown in Figure 6 is recommended when using a ceramic resonator. Table 3 lists the recommended feedback capacitance and resistance values. The manufacturer of the particular ceramic resonator being considered should be consulted for specific information. 3.2 MISCELLANEOUS REGISTER MISCELLANEOUS REGISTER (MISCR) Address: 003Fh -- Read/Write Reset Value: 0010 1010 (2Ah) 7 RXLAT RXITE 1 TXEN HVSEL VSYNC INT 0 WDGF Table 2. Recommended Values for Crystal Resonator RSMAX C0 C1 C OSCin C OSCout RP Q 2MHz 400 5 8 15-40 15-30 10 30 4MHz 75 7 12 15-30 15-25 10 40 8MHz 60 10 15 15-25 15-20 10 60 Unit pF nF pF pF M 103 b7 = RXLAT: Falling edge detector latch This bit is set when a falling edge occurs on the RX pin on Port C. It may be cleared by S/W. This bit can be used to monitor I2C activity or implement RS232 RX S/W emulation. b6 = RXITE: Interrupt enable control bit Read/Write. If this bit is set, then an interrupt is generated when RXLAT is set. No other interrupt is generated. b5 = UNUSED Read as "1" when accessed. b4 = TXEN This bit (read/write) enables the OCMP1 Output to be connected to the TX pin. This function is enabled when the bit is set. b3 = HVSEL: Alternate Sync Input Select This bit selects between the two set of Horizontal and Vertical Sync inputs. HVSEL= 0: HSYNCI2 (PC1) and VSYNCI2 (PD4) pins are selected as HSYNCI and VSYNCI inputs respectively. HVSEL= 1: HSYNCI1 and VSYNCI1 pins are selected as HSYNCI and VSYNCI inputs respectively. b2 = VSYNC: Internal Vsync This bit (Read-Only) shows the state of the VSync input to the Sync Processor. b1 = INT: Interrupt Request This bit sets the interrupt configuration for the PORT B wake-up Interrupt Request: INT = 0: selects the falling edge option only, INT = 1: selects the falling edge or low-level option. WARNING. This bit can only be written ONCE after reset. Writing to INT is disabled after the first write to the Miscellaneous Register. Bit manipulation instructions should be used with extreme caution when writing to this register. b0 = WDOGF: Watchdog flag Set by WDOG reset, cleared by S/W(a write of zero) or POR. This flag is useful to dinstinguish Power On Reset and Watchdog Reset. 3.1.4 External Clock An external clock may be applied to the OSCin input with the OSCout pin not connected, as shown on Figure 4. The tOXOV and tILCH specifications do not apply when using an external clock input. The equivalent specification of the external clock source should be used instead of t OXOV or tILCH. See Section 6.5 CONTROL TIMING. Table 3. Recommended Values for Ceramic Resonator R SMAX C0 C1 C OSCin C OSCout RP Q 2-8MHz 10 40 4.3 30 30 1-10 1250 Unit pF nF pF pF M 18/119 18 ST7272 3.3 RESETS 3.3.1 Introduction There are three sources of Reset: - External Reset (Reset pin) - Power-On Reset (Internal source) - Watchdog (Internal Source) The starting address of the Reset Service Routine is located at address vector 7FFEh-7FFFh. 3.3.2 External Reset The RESET pin is both an input and an open-drain output with integrated pull up resistor. When the Watchdog Reset is active, the Reset pin is driven low to reset the application. 3.3.3 Power-On Reset Following power-up, or when exiting the HALT Mode, a delay period is initiated to allow for Reset State Recovery or oscillator stabilisation. This delay is 4096 CPU clock cycles. At the end of the Power-On Reset cycle, the MCU may be held in the Reset condition by an External Reset signal. The RESET pin may thus be used to ensure V DD has risen to a point where the MCU can operate correctly before the User program is run. During Power-on, the RESET pin is pulled low, thus permitting the MCU to reset other devices. Power-On Reset is used exclusively for power-up and should not be used in order to attempt to detect any drop in the power supply voltage. Table 4. Sections affected by Reset, WAIT and HALT. Section Timer Prescaler reset to zero Timer Counter set to FFFCh All Timer enable bit set to 0 (disable) Data Direction Registers set to 0 (as Inputs) Set Stack Pointer to 01FFh Force Internal Address Bus to restart vector 7FFEh,7FFFh Set Interrupt Mask Bit (I-Bit, CCR) to 1 (Interrupt Disable) Set Interrupt Mask Bit (I-Bit, CCR) to 0 (Interrupt Enable) Reset HALT latch Reset INT latch Reset WAIT latch Disable Oscillator (for 4096 cycles) Set Timer Clock to 0 Watchdog counter reset Watchdog register reset EEPROM control bits reset PWM/BRM registers reset EWPCC DAC register reset SYNC registers reset Port data registers X X X X X X RESET X X X X X X X X X X POR X X X X X X X X X X X X X X X X X X X X X X X X WAIT HALT 19/119 19 ST7272 RESETS (Cont'd) . Figure 8. Reset Timing t DDR VDD OSCin t OXOV CPU CLOCK PC 7FFE 7FFF WATCHDOG RESET EXTERNAL RESET POWER ON RESET VR01969 Figure 9. Reset Block Diagram INTERNAL RESET OSCILLATOR SIGNAL to ST7 COUNTER RESET RESET VDD 300K WATCHDOG RESET OR DLPSS VR2062C 20/119 20 ST7272 3.4 WATCHDOG TIMER SYSTEM (WDG) 3.4.1 Introduction The Watchdog timer is used to detect the occurence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter's contents before it is decremented to zero. 3.4.2 Functional Description The counter is decremented every 49,152 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments, ranging from 12 msec to 784 msec at 8 MHz oscillator frequency, depending on the value loaded in bits 0-5 of the Watchdog register. The application program must be written so that the Watchdog register is reloaded at regular intervals during normal operation. The Watchdog is not activated automatically on Reset, and must be activated by the user program if required. Once activated it cannot be disabled, except by a Reset. Table 5. Watchdog Timing (fOSC = 8 MHz) WDG Register initial value FF C0 WDG timeout period (ms) 784 12 high state, an internal pull-up resistor of about 300K is connected to the Reset pin. This resistor can be pulled low by external circuitry to reset the device. The Watchdog delay time is defined by bits 5-0 of the Watchdog register; bit 6 must always be set in order to avoid generating an immediate reset. Conversely, this can be used to generate a software reset (bit 7 = 1, bit 6 = 0). Once bit 7 is set, it cannot be cleared by software: i.e. the Watchdog cannot be disabled by software without generating a Reset. The Watchdog timer must be reloaded before bit 6 is decremented to "0" to avoid a Reset. Following a Reset, the Watchdog register will contain 7Fh (bits 0-6 = 1, bit 7 = 0). If the Watchdog is activated, the HALT instruction will generate a Reset. If the circuit is not used as a Watchdog (i.e. bit 7 is never set), bits 6 to 0 may be used as a simple 7bit timer, for instance as a real time clock. Since no interrupt will be generated under these conditions, the Watchdog register must be monitored by software. 3.4.3 Watchdog Register Register Address: 0024h -- Read/ Write Reset Value: 0111 1111 (7Fh) 7 WDGA T6 T5 T4 T3 T2 T1 0 T0 During the Watchdog initiated Reset cycle, the device Reset pin acts as an output that is pulsed low for 3 machine cycles (6 oscillator cycles). In its b7 = WDGA: Activation bit (is active if set) b6-0 =T6-T0: 7 bit timer (Msb to Lsb) 21/119 21 ST7272 3.5 INTERRUPTS 3.5.1 Introduction The MCU may be interrupted by six maskable hardware interrupts (generated by PORT B, RX, DDC and TIMER) and a non-maskable software interrupt (TRAP). Reset also generates a nonmaskable interrupt. These interrupt sources, together with their vector addresses and priorities are illustrated in Table 6 below. The Interrupt processing flowchart is shown in Figure 10. Maskable interrupts must be enabled in order to be serviced, however disabled interrupts can be latched and processed when next enabled. When an interrupt needs servicing, the PC, as well as the X, A and CC registers are saved on the stack, and the Interrupt Mask (I bit of the Condition Code Register) is set to prevent further interrupts. The Y register is not automatically saved. The PC is then loaded with the interrupt vector of the interrupt to be serviced and the interrupt service routine is executed. The interrupt service routine should end with an IRET instruction, which causes the contents of the registers to be recovered from the stack and normal processing to be resumed. The I bit is then cleared if, and only if, the corresponding bit stored in the stack is zero. Though several interrupts may be simultaneously pending, a priority order is defined and they are dealt with in this order. The RESET pin has the highest priority. If the I bit is set, TRAP is the only enabled interrupt (Reset is, of course always enabled). All interrupts allow the processor to leave the Wait power saving mode. Only the external interrupt causes the processor to leave Halt mode. 3.5.2 Software Interrupt The software interrupt is generated by the executable instruction TRAP. The interrupt is recognized when the TRAP instruction is executed, regardless of the state of the I bit, and the corresponding service routine will be executed. Table 6. Interrupt Mapping and Priorities Vector Address 7FFE-7FFF h 7FFC-7FFD h 7FFA-7FFB h 7FF8-7FF9 h 7FF6-7FF7 h 7FF4-7FF5 h 7FF2-7FF3 h 7FF0-7FF1 h Interrupt Source RESET or POWER-ON (POR) SOFTW ARE interrupt (TRAP) PORT B Wake up RX falling edge interrupt ICAP Input capture OCMP Output compare TOF Timer overflow DDC/DMA Masked by none none I-Bit I-Bit I-Bit I-Bit I-Bit I-Bit Priority highest 3.5.3 Port B Interrupt The PORTB Interrupt can be generated by a falling edge or by a low level on any pin of Port B, if it is defined as an interrupt source. When an enabled interrupt occurs, normal processing is suspended at the end of the current instruction execution and the corresponding interrupt service routine is executed. If the interrupt is disabled (I high), the triggering edge of the wake-up interrupt source is internally latched and the interrupt remains pending to be processed as soon as the interrupt is next enabled. This internal latch is cleared in the first part of the service routine. Therefore, only one external interrupt can be latched and serviced at a time. 3.5.4 RX interrupt The RX pin can generate an interrupt on a falling edge, if enabled via the RXITE bit in the Miscellaneous register and the I bit in the CCR. The RX service routine must reset the cause of this interrupt by clearing the RXLAT or RXITE bits in the Miscellaneous register. This function allows software implementation of a basic asynchronous serial communications interface with minimum processor overhead, by detecting a Start condition automatically. 3.5.5 Timer Interrupt Five interrupt flags in the Timer Status Register can generate a timer interrupt if both the I bit of the CCR is reset and if the corresponding enable bit in the Timer Control Register is set, otherwise the interrupt is latched and remains pending. The timer service routine must determine the source of the interrupt by examining the flags and status bits. The general sequence for clearing an interrupt is an access to the status register while the flag is set, followed by reading or writing an associated register. Note that the clearing sequence resets the internal latch. A pending interrupt will therefore be lost if the clearing sequence is executed. Lowest 22/119 22 ST7272 INTERRUPTS (Cont'd) Figure 10. Interrupt Processing Flowchart INTERRUPT TRAP N Y I BIT = 1 N Y PUSH PC,X,A,CC ONTO STACK SET I BIT TO 1 FETCH NEXT INSTRUCTION OF APPROPRIATE INTERRUPT SERVICE ROUTINE LOAD PC WITH APPROPRIATE INTERRUPT VECTOR (1) EXECUTE INSTRUCTION VR01172B Note 1. See Table 6 23/119 23 ST7272 3.6 POWER SAVING MODES 3.6.1 Introduction Two special power saving operating modes are available: WAIT Mode and HALT Mode. These are described in the following paragraphs. Table 4 lists the various sections affected by the low power modes. 3.6.2 Wait Mode The WAIT instruction places the MCU in a low power consumption mode by stopping the CPU. Figure 11. Wait Mode Flow Chart All peripherals remain active and the I bit (CC Register) is cleared, so as to enable all interrupts. All other registers and memory remain unchanged. The MCU will remain in WAIT mode until an Interrupt or Reset occurs, whereupon the Program Counter branches to the starting address of the Interrupt or Reset Service Routine. This is illustrated in Figure 11 below. WAIT WAIT ACTIVE OSCILLATOR AND PERIPHERALS CLOCKS ACTIVE PROCESSOR CLOCK STOPPED N RESET N EXTERNAL INTERRUPT Y Y RESTART PROCESSOR CLOCK N PERIPHERAL INTERRUPT FETCH RESET VECTOR OR SERVICE INTERRUPT Y VR02062D 24/119 24 ST7272 POWER SAVING MODES (Cont'd) 3.6.3 Halt Mode The HALT instruction places the MCU in its lowest power consumption mode. In HALT mode the internal oscillator is turned off, causing all internal processing to be halted. During HALT mode, the I bit in the CC Register is cleared so as to enable External Interrupts. All other registers and memory remain unaltered and all Input/Output lines remain unchanged. This Figure 12. Halt Mode Flow Chart state will endure until an External Interrupt or Reset is generated, whereupon the internal oscillator is turned on. A delay of 4096 CPU clock cycles is initiated prior to restarting, in order to allow the oscillator to stabilize. The External Interrupt or Reset causes the Program Counter to be set to the address of the corresponding Interrupt or Reset Service Routines. WAIT HALT STOP OSCILLATOR AND ALL CLOCKS CLEAR I-BIT N RESET N EXTERNAL INTERRUPT Y OSCILLATOR IN SLOW MODE Y TURN ON OSCILLATOR WAIT FOR 4096 CPU CLOCK TIME DELAY FETCH RESET VECTOR OR SERVICE INTERRUPT VR02062E 25/119 25 ST7272 4 ON-CHIP PERIPHERALS 4.1 EEPROM (EEP) 4.1.1 Introduction The on-chip EEPROM provides non-volatile storage for user data. It is read as a normal Read-Only memory location (user programs cannot however be run from EEPROM). Programming and erasure are controlloed by means of the EEPROM control registers, and 8 data latches allow simultaneous erase or write operations to be carried out on up to 8 EEPROM memory bytes simultaneously. However, all addressed memory bytes must be on the same row of the EEPROM memory array, that is up to eight bytes with the address bits A7, A6, A5, A4 and A3 constant, and with A2, A1 and A0 selecting the address(es) to be written within the row. The EEPROM cell includes an internal charge pump to avoid the need of an external high voltage supply for erasure and programming cycles. The programming pulse duration is automatically controlled to achieve the shortest possible programming time. Figure 13. EEPROM Block Diagram 4.1.2 Functional Description As shown in See ". EEPROM Block Diagram" on page 26., the EEPROM is organised as an 8 column by 32 row array. The row is selected by the A7, A6, A5, A4, A3 bits. Each column is associated with an 8-bit data register. 4.1.2.1 Read Operation The EEPROM may be read as a normal ROM location when the E2LAT bit in the Control Register is cleared to "0". The E2PGM and E2ERA bits are also forced to "0" when E2LAT is at "0". 4.1.2.2 Write/Erase Operation When E2LAT is set to "1", a write to an EEPROM location latches the data written in the 8-bit register corresponding to the decoded column and sets an internal flag for the decoded row. As there are 8 columns in each row, up to 8 locations (having the same A7, A6, A5, A4, A3 address bits) can be simultaneously written or erased. HIGH VOLTAGE PUMP EEPROM CONTROL REGISTER RESERVED NU NU E2ERA E2LAT E2PGM 32 ROWS LATCH EEPROM MEMORY ARRAY ADDRESS BUS ADDRESS DECODER 8-BIT REGISTER AMPLI 8 COLUMNS VR001106 26/119 26 DATA BUS ST7272 EEPROM (Cont'd) To erase bytes, the E2LAT and E2ERA bits are set, and the EEPROM addresses to be erased are written to (the data value is not significant). The E2PGM bit is set to turn the charge pump on. To write bytes, the E2LAT bit is set, and data is written to the appropriate EEPROM address(es). The E2PGM bit is set to turn the charge pump on. After a time TPROG, the programming operation is automatically terminated. E2LAT, E2PGM and E2ERA bits are reset. WARNING: A minimum delay of TDIS must be respected after a programming operation (the falling edge of E2LAT) before the next read or write of the EEPROM. This time is required to discharge the high voltage in the array. 4.1.3 Application Notes - Each EEPROM bank is controlled by an independent EEPROM Control Register. Please refer to the Memory Map for the four EEPROM memory block locations. - It is mandatory to erase bytes before writing them. - When E2LAT is high, access to the EEPROM array is not possible. - It is possible to stop a programming sequence at any time by resetting the E2LAT bit. In this case, the programmed data value is not guaranteed. A minimum delay of TDIS must be respected before the next read or program cycle. 4.1.4 Register Descriptions DDC-EEP CONTROL REGISTER(CR0) GP1-EEP CONTROL REGISTER(CR1) GP2-EEP CONTROL REGISTER(CR2) EWPCC EEP CONTROL REGISTER(CR3) Read/Write EEPROM Bank DDC GP1 GP2 EWPCC EEPROM Address 0280-02FF 0300-03FF 0400-04FF 0500-05FF Register Name CR0 CR1 CR2 CR3 Register Address 000Eh 000Fh 0010h 0011h Reset Value: 0000 0000 (00h) 7 Res. Res. Res. E2ERA E2LAT 0 E2PGM These registers contain the bits required to read, erase and program the EEPROM memory banks. They are defined as follow: b7-5 = Reserved, must be set to "0" b4,3 = Unused, read as "0" b2 = E2ERA: EEPROM Erase. E2ERA must be set for an erase operation. It must be set after or at the same time as E2LAT. It cannot be changed once an EEPROM address is selected. It is held low when E2LAT is low. It is therefore automatically reset when E2LAT is reset. b1 = E2LAT: EEPROM Latch Enable. When E2LAT is reset, data can be read from the EEPROM. When it is set and E2PGM reset, a write into the EEPROM array causes the data to be latched, according to the address into one of 8 data registers. An additional internal flag is latched to select the row. The selected columns and row determine the locations involved in the next erase or programming operation. E2LAT is automatically cleared at the end of each programming operation. It can be reset by software, but in this case the programming result is not guaranteed. E2ERA and E2PGM are forced low when E2LAT is low b0 = E2PGM: EEPROM Program Mode. This bit allows the internal charge pump to be switched on or off. When set, the charge pump generator is on and the high voltage is applied to the EEPROM array. When low, the charge pump generator is off. E2PGM can only be reset by resetting E2LAT. 27/119 27 ST7272 EEPROM (Cont'd) Figure 14. Basic EEPROM Programming Flow-chart E2LAT = 0 E2PGM = 0 E2ERA = 0 After t DIS E2LAT = 1 E2LAT = 1 E2ERA = 1 Write Byte(s) in EEPROM Write Byte(s) in EEPROM E2PGM = 1 (Start Pumping) (Writing in Progress) E2PGM = 1 (Start Pumping) (Erasing in Progress) Wait for E2LAT = 0 (after t PROG ) Wait for E2LAT = 0 (after t PROG ) After tDIS Check Written Byte(s) (Optional) END VR01963 Figure 15. EEPROM Programming Timing Diagram read operation forbidden read operation allowed VPP tPROG tDIS E2LAT 28/119 28 ST7272 4.2 I/O PORTS 4.2.1 Introduction The I/O ports allow data transfer by means of digital inputs and outputs and, for specific pins, input of analog signals or Input/Output of dedicated signals relating to the the on-chip peripherals (e.g. DDC, EWPCC, Timer, etc.). 4.2.2 Functional Description Each pin of the I/O Ports can be individually configured under software control as either input or output. Ports A and B are 8-bit ports, Port C is a 6bit port and Port D is a 5-bit port. Each bit of a Data Direction Register (DDR) relates to the corresponding I/O pin on the associated port. A bit must be set to configure its associated pin as an output, and must be cleared to configFigure 16. Typical I/O Circuit ure the pin as an input. The Data Direction Registers may be read and written. The typical I/O circuit is illustrated schematically in Figure 16. A write to an I/O port updates the port data register even if it is configured as an input. A read of an I/O port returns either the data latched in the port data register (pins configured as output) or the value at the I/O pin (pins configured as input). At power-on or following an external reset, all DDR registers are cleared, which configures Ports B, C and D as inputs with pull-ups and Port A as inputs without pull-ups. The port data registers are not initialized. Thus, the I/O port should be written to before setting the DDR bit to avoid undefined output levels. DATA DIRECTION REGISTER BIT INTERNAL CONNECTIONS LATCHED OUTPUT DATA BIT INPUT REG. BIT INPUT I/O OUTPUT I/O PIN TYPICAL PORT DATA DIRECTION REGISTER TYPICAL PORT REGISTER 7 DDR 7 6 DDR 6 5 DDR 5 4 DDR 4 3 DDR 3 2 DDR 2 1 DDR 1 0 DDR 0 PIN P-7 P-6 P-5 P-4 P-3 P-2 P-1 P-0 VR000084 29/119 29 ST7272 I/O PORTS (Cont'd) 4.2.2.1 Port A Each Port A bit can be defined as an Input line (no pull-up) or as an open-drain Output. 4.2.2.2 Port B Any bit of Port B bit may be used as an Analog input to the Analog to Digital converter, by selecting each individual bit independently in the Port B Configuration Register. When the Analog input function is selected, the pull-up on the respective pin of Port B is disconnected and both the Data and Direction (DR and DDR) registers of the respective pin are reset. Any further accesses to this particular DDR bit is blocked until the pin status is reset to normal I/O. Port B bits can also be configured on a bit basis as a wake-up interrupt input with an internal pull-up resistor. This mode is enabled by setting the corresponding Port B bit as a digital input (its bit in DDR reset and its Analog function disabled) and the corresponding bit in the Port B Data Register must be set. When this bit is subsequently forced low, an interrupt will be generated according to the status of the INT bit in the Miscellaneous Register. Port B, bit 0 is only available for output if the EastWest Pin-Cushion Correction circuit (EWPCC) is not used. If the EWPCC function is selected, Port B bit 0 MUST be set as input to enable the V FBACK timing input. All unused I/O lines should be tied to an appropriate logic level (either VDD or VSS). 4.2.2.3 Port C The available Port C pins may be used as general purpose I/O, as the alternate HSYNCI2 Sync Input, HFBACK input or as I/O pins for the on-chip DDC and Timer Output Compare. When used as digital Input, pull-up resistors on PC 4,5 can be switched on by setting the PUPC bits of the ProPORT A PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 I/O Input without pull-up without pull-up without pull-up without pull-up without pull-up without pull-up without pull-up without pull-up Output open drain open drain open drain open drain open drain open drain open drain open drain grammable Input/Output Configuration Register (PCR). Port C, bit 0 is switched from the normal I/O functionality to the output of the Timer Output Compare signal by resetting the OCOP bit of the PCR. This pin is also the HFBACK input. Port C, bit 1 is also the alternate HSYNCI2 input of the Sync Processor block. Port C bits 2,3 are always open-drain outputs or inputs without pull-up resistors. The default condition of open drain output allows software emulation of communication using the I2C bus protocol on PC4,5. 4.2.2.4 Port D The Port D I/O pins are normally used for input and output of video synchronization signals to the Sync Processor, but are set as I/O inputs with pull-ups on reset. The I/O mode can be set individually for each port bit to Input with pull-up or push-pull output through the Port D DDR. The support the Sync Processor, the configuration requires that the SYNOP bit of the PCR be reset; this enables Port D bits 0, 1 and 2 as sync outputs. Port D, bit 4 is switched to the alternate VSYNCI Input (VSYNCI2) by resetting the HVSEL bit of the Miscellaneous Register. Note : Since these inputs are switched from normal I/O functionality, the video synchronization signals may also be monitored directly through the Port D Data Register for such tasks as checking for the presence of video signals or checking the polarity of Horizontal and Vertical synchronization signals (when the Sync Inputs are switched directly to the outputs using the Sync Processor multiplexers). Table 7. Port A Possible I/O Configuration. Alternate Function Signal BLK Condition BLKEN = 1 30/119 30 ST7272 I/O PORTS (Cont'd) Table 8. Port B Possible I/O Configurations. PORT B Input I/O Output signal analog input (ADC) (without pull-up) with pull-up wake up interrupt push-pull (input with pull-up) VFBACK (input with schmitt trigger) analog input (ADC) (without pull-up) PB1 with pull-up push-pull wake up interrupt (input with pull-up) analog input (ADC) (without pull-up) PB2 with pull-up push-pull wake up interrupt (input with pull-up) analog input (ADC) (without pull-up) PB3 with pull-up push-pull wake up interrupt (input with pull-up) analog input (ADC) (without pull-up) PB4 with pull-up push-pull wake up interrupt (input with pull-up) analog input (ADC) (without pull-up) PB5 with pull-up push-pull wake up interrupt (input with pull-up) analog input (ADC) (without pull-up) PB6 with pull-up push-pull wake up interrupt (input with pull-up) analog input (ADC) (without pull-up) PB7 with pull-up push-pull wake up interrupt (input with pull-up) Alternate Functio n Conditi on AD0=1 (PBICFGR) PBDDR0=0 AD0=0 (PBICFGR) PBDR0=1 AD1=1 (PBICFGR) PBDDR1=0 AD1=0 (PBICFGR) PBDR1=1 AD2=1 (PBICFGR) PBDDR2=0 AD2=0 (PBICFGR) PBDR2=1 AD3=1 (PBICFGR) PBDDR3=0 AD3=0 (PBICFGR) PBDR3=1 AD4=1 (PBICFGR) PBDDR4=0 AD4=0 (PBICFGR) PBDR4=1 AD5=1 (PBICFGR) PBDDR5=0 AD5=0 (PBICFGR) PBDR5=1 AD6=1 (PBICFGR) PBDDR6=0 AD6=0 (PBICFGR) PBDR6=1 AD7=1 (PBICFGR) PBDDR7=0 AD7=0 (PBICFGR) PBDR7=1 31/119 PB0 31 ST7272 I/O PORTS (Cont'd) Table 9. Port C Possible I/O Configurations PORT C I/O Input with pull-up Output push-pull Alternate Function Signal OCMP (push-pull) PC0 HFBACK (input with schmitt trigger) PC1 with pull-up push-pull HSYNCI2 (input with schmitt trigger) SCL1 PC2 input without pull-up open-drain (input with schmitt trigger or open drain output) RX (input) SDA1 PC3 input without pull-up open-drain (input with schmitt trigger or open drain output) TX (input) PC4 input with or without pull-up depending on PUPC (PCR) input with or without pull-up depending on PUPC (PCR) open-drain DDC enable TXEN DDC enable Condition OCOP(PCR)=0 - PC5 open-drain - - Table 10. Port D Possible I/O Configurations PORT D PD0 PD1 PD2 PD3 PD4 I/O Input with pull-up with pull-up with pull-up with pull-up with pull-up Output push-pull push-pull push-pull push-pull push-pull Alternate Function Signal CSYNCI (input with pull-up) HSYNCO (push pull output) VSYNCO (push pull output) CLMPO (push pull output) VSYNCI2 (input with pull-up) I/O Pin Functions The I/O pin is in input mode. Data is written into the data latch Data is written into the data latch and output to the I/O pin The state of the I/O pin read. The I/O pin is in an output mode.The data latch is read Condition SYNOP=0 (PCR) SYNOP=0 (PCR) SYNOP=0 (PCR) - R/W 0 0 1 1 DDR 0 1 0 1 32/119 32 ST7272 I/O PORTS (Cont'd) 4.2.3 Register Descriptions DATA REGISTERS (PADR) Port A -- Address: 0000 h (PBDR) Port B -- Address: 0001 h (PCDR) Port C -- Address: 0002 h (PDDR) Port D -- Address: 0003 h Read/Write Reset Value: Undefined DATA DIRECTION REGISTERS (PADDR) Port A -- Address: 0004h (PBDDR) Port B -- Address: 0005h (PCDDR) Port C -- Address: 0006h (PDDDR) Port D -- Address: 0007h Read/Write Reset Value: 0000 0000 (00h) (as inputs) PORT B CONFIGURATION REGISTER (PBICFGR) Address: 003C h -- Read/Write Reset Value: 0000 0000 (00h) 7 AD7 AD6 AD5 AD4 AD3 AD2 AD1 0 AD0 PROGRAMMABLE INPUT/OUTPUT CONFIGURATION REGISTER (PIOCFGR) Address: 003D h -- Read/Write Reset Value: 1111 1000 (F8 h)) 7 Res . CLMO P OCO P SYNO P POC 2 POC 1 0 POC 0 PUPC Bit-7= Reserved. b6 = CLMOP: Clamping Signal Output Select. This bit selects either the PD3 I/O Pin Option or the output of the Clamping signal. CLMOP = 0: Clamping Signal CLMOP = 1: PD3 as Pull-up Input or Push-pull Output b5 = OCOP: Timer Output Compare Select. This bit selects either the PC0 I/O Pin Option or the output of the Timer Output Compare. OCOP = 0: Timer Output Compare OCOP = 1: PC0 as pull-up Input or push-pull Output b4 = SYNOP:SYNC Processor Function Select. This bit selects either the Sync Processor or PD0, PD1, PD2 I/O Pin Options. SYNOP = 0: PD0 = CSYNCI, PD1 = HSYNCO and PD2 = VSYNCO SYNOP = 1: PD0/PD1/PD2 as pull-up Inputs or push-pull Outputs Note. HSYNC O and VSYNCO can be directly read as Port bits by configuring PD1 and PD2 as inputs. b7-0 = AD7-AD0: Port B Digital/Analog Input Configuration Bits. When AD#i is set (i = 7-0), the pullup on the respective pin #i of Port B is disconnected and the pin is configured as analog input; otherwise the pull-up is connected and the pin configured as a digital input (RESET condition) with no power consumption in the A/D channel. b3 = PUPC: PORT C Input Configuration Bit. This bit selects the input configuration for present bits of I/O Port C (PC4:5). PUPC = 1: Port C with Pull-up PUPC = 0: Port C without Pull-up b2-b0 = POC2-POC0: PWM/BRM Output Configuration Bits. These bits select the PWM/BRM output configuration. Table 11. PWM Output Configurations. PWM Group Channels A2 DA1.. D3-6 B1 DA7-11 B2 DA12-DA17 P0C0 P0C1 P0C2 O push-pull push-pull push-pull Value 1 open drain open drain open drain Note: In the case of incomplete ports (port C and port D),non-implemented bits are read as '0' whenever accessed 33/119 33 ST7272 4.3 16-BIT TIMER 4.3.1 Introduction The 16-bit programmable timer consists of a 16-bit free running counter complete with prescaler and the necessary control logic to handle two input capture and two output compare registers. The timer may be used for many purposes, amongst which period measurement of input signals and generation of output waveforms. The two input capture functions are dedicated to the Sync Processor, and are internally connected to this source. They are thus not available for timing other external signals. When used with an 8MHz oscillator frequency, the timer offers a resolution of 0.5 us. 4.3.2 Functional Description Since the timer has a 16-bit architecture, each of its specific functional blocks comprises two registers. These registers contain the high order and low order byte of that function. However any access to the high order byte inhibits that specific timer capability until the low order byte is also accessed. Note: correct software procedures should set the I bit of the Condition Code Register before accessing the high order byte to prevent an interrupt from occurring between the accesses to the high and low order bytes of any register. returns the MSB of the count value and causes the LSB to be transferred into a buffer. The buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MSB several times. The read sequence is completed by reading the free running counter LSB, which actually returns the buffered value. The free running counter is configured to FFFCh during reset, after the RESET line goes high. During a power-on reset (POR), the counter is also configured to FFFCh and begins running after the oscillator start-up delay. When the counter rolls over from FFFFh to 0000h, the Timer Overflow flag (TOF) of the Timer Status Register (SR) is set. A timer interrupt is then generated if the TOIE enable bit of the Timer Control Register (TCR) is set, provided the I bit of the CCR is cleared. If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true. The interrupt request is cleared by reading SR while TOF is set followed by an access (read or write) to the LSB of the Counter Register. The TOF flag is not affected by accesses to the Alternate Counter Register. This feature allows simultaneous use of the overflow function and reads of the free running counter at random times (for instance, to measure elapsed time) without risking clearing the TOF flag unintentionally. Accesses to the timer without the intention of servicing the TOF flag should therefore be performed to the Alternate Counter Register while only the TOF service routine accesses the Counter Register. The free-running counter can be reset under software control. This is performed by writing to the LSB of either the Counter Register or the Alternate Counter Register. The counter and the prescaler are then configured to their reset conditions. This reset also completes any 16-bit access sequence. All flags and enable bits are unchanged. The value in the counter registers repeats every 131,072 internal processor clock cycles (32 ms for fCPU = 4 MHz). The counter increment is triggered by a falling edge of the CPU clock. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU woken by an interrupt) or from the reset count (MCU woken by a reset). 4.3.3 Counter The key element of the programmable timer is a 16-bit free running counter, preceded by a prescaler which divides the internal clock by two giving an operational frequency of 2MHz for an oscillator frequency of 8MHz. Software can read the counter at any time without affecting its value. It can be read from two locations, the Counter Register (0018h, 0019h) and Alternate Counter Register (001Ah, 001Bh). The only difference between these two read-only registers is the way the overflow flag TOF is handled during a read sequence. A read sequence containing only a read of the least significant byte of the free running counter (from either the Counter Register or the Alternate Counter Register) will receive the LSB of the count value at the time of the read. A read of the most significant byte (from either the Counter Register or the Alternate Counter Register) simultaneously 34/119 34 ST7272 16-BIT TIMER (Cont'd) Figure 17. Timer Block Diagram ST7 INTERNAL BUS INTERNAL PROCESSOR CLOCK MCU-PERIPHERAL INTERFACE HIGH BYTE HIGH BYTE HIGH BYTE HIGH BYTE HIGH BYTE 16 16 16 EDGE DETECT CIRCUIT 2 EDGE DETECT CIRCUIT 1 IC_B IC_A D LATCH CLK 7 6 5 4 3 TIMER STATUS ICF1 OCF1 TOF ICF2 OCF2 2 0 0 1 0 0 OCMP 2 0 1 LOW BYTE LOW BYTE LOW BYTE LOW BYTE LOW BYTE 0 TIMER REGISTER TIMER INTERNAL INTERRUPT VR01964 8 8-BIT BUFFER 1/2 16-BIT FREE RUNNING COUNTER COUNTER ALTERNATE REGISTER OUTPUT COMPARE REGISTER1 OUTPUT COMPARE REGISTER2 INPUT CAPTURE REGISTER1 INPUT CAPTURE REGISTER2 16-Bit INTERNAL TIMER BUS OVERFLOW DETECT CIRCUIT OUTPUT COMPARE CIRCUIT REGISTER 7 6 5 4 0 3 FOLV1 ICIE OCIE TOIE IEDG1 OLVL1 CONTROL 35/119 35 ST7272 16-BIT TIMER (Cont'd) 4.3.4 Input Capture. The ST7272 features two input capture registers and one input capture interrupt enable bit. The input capture inputs IC_A and IC_B are connected through the VSYNCI and HSYNCI (OR CSYNCI) input pins respectively. When the SYNC processor is not being used, these pins may be used for the timer external input capture circuits. The input on HSYNCI may optionally be passed through a 256 prescaler before being passed to the IC_B input capture. Input Capture Register 1(ICR1) is a 16-bit register consisting of two 8-bit registers: the most significant byte register (ICHR1), located at 0014h, and the least significant byte register (ICLR1) located at 0015h. ICR1 is a read-only register used to latch the value of the free running counter after a defined transition is sensed by the input capture edge detector IC_A. This transition is software programmable through the IEDG1 bit of the Timer Control RegisFigure 18. Timer Timing Diagram ter (TCR). When IEDG1 is set, a rising edge triggers the capture; when IEDG1 is low, the capture is triggered by a falling edge. Care must be taken with the external circuitry to avoid unwanted interrupts when changing the interrupt edge. When an input capture occurs, the ICF1flag in the Timer Status Register (SR) is set. An interrupt is requested if the interrupt enable bit ICIE of TCR is set, provided the I bit of the CCR is cleared. Otherwise, the interrupt remains pending until both conditions become true. It is cleared by reading the Timer Status Register SR followed by an access (read or write) to the LSB of ICR1. The result stored in ICR1 is one more than the value of the free running counter on the rising edge of the internal processor clock preceding the active transition on IC_A. This delay is required for internal synchronization. Therefore, the timing resolution of the input capture system is one count of the free running counter, i.e. 2 internal clock cycles. 1 CPU CLOCK 2 3 4 5 6 7 8 9 10 11 INTERNAL RESET INTERNAL TIMER CLOCKS T10 COUNTER REGISTER FFFDh FFFEh FFFFh 0000h 0001h TOF FLAG VR001175 36/119 36 ST7272 16-BIT TIMER (Cont'd) The free running counter is transferred to ICR1 on each proper signal transition, regardless of whether the Input Capture Flag ICF1 is set or cleared. The ICR1 always contains the free running counter value which corresponds to the most recent input capture. After reading the MSB of ICR1 (ICHR1), counter transfer of input capture is inhibited until the LSB of ICR1 (ICLR1) is also read. This characteristic forces the minimum pulse period attainable to be determined by the time required to service the interrupt and to execute the interrupt routine. Reading ICLR1 does not inhibit counter transfer. Again, minimum pulse periods are the ones which allow software to read the least significant byte and perform needed operations. There is no conflict between reading ICR1 and the running counter transfer since they occur on opposite edges of the internal processor clock. The contents of ICR1 are undetermined at poweron and are not affected by an external reset. Hardware circuitrymust provide protection from generating a spurious input capture when changing the edge sensitivity option of the IC_A input through the IEDG1 bit. Figure 19. Input Capture Timing Diagram CPU CLOCK During HALT mode, if at least one valid input capture edge occurs at the IC_A input, the input capture detect circuitry is armed. This action does not set any timer flags nor will it "wake-up" the MCU. If the MCU is woken up by an interrupt, there will be an active input capture flag and data from the first valid edge that occurred during HALT mode. If HALT mode is exited by a reset, the input capture detect circuitry is reset and thus any active edge that occurred during HALT mode will be lost. Input Capture Register 2. (ICR2) is a 16-bit register comprising two 8-bit registers: the most significant byte register (ICHR2), located at 001Ch, and the least significant byte register (ICLR2) located at 001Dh. The previous description for Input Capture Register 1 is also applicable to Input Capture Register 2, with the exception that Input Capture Register 2 is triggered only on a negative edge on input IC_B (and with the substitution of the appropriate suffix in the bit and register names. 4.3.5 Output Compare There are two output compare registers: Output Compare Register 1 and 2 (OCR1 and OCR2). T10 TIMER INTERNAL CLOCKS T11 COUNTER REGISTER FF01h FF02h FF03h IC INPUT (see note) ICAP FLAG ICAP REGISTER FF03h VR01965 37/119 37 ST7272 16-BIT TIMER (Cont'd) They can be used for several purposes, such as controlling an output waveform or indicating when a period of time has elapsed. The OCMP1 pin is associated with output compare 1; no pin is associated with Output Compare 2 which, however, may be usedto generate timer interrupts. The Output Compare Registers are unique because all bits are readable and writable and are not affected by the timer hardware or reset. If a compare function is not used, the two bytes of the corresponding Output Compare Registers can be used as storage locations. Note that the same output compare interrupt enable bit is used for both output compares. Output Compare Register 1. The Output Compare Register 1 (OCR1) is a 16-bit register, consisting of two 8-bit registers: the most significant byte register (OCHR1) at address 0016h and the least significant byte register (OCLR1) at address 0017h. The content of OCR1 is compared with the content of the free running counter once during every timer clock cycle, i.e. every 2 internal processor clock periods. If a match is found, the Output Compare Flag OCF1 of the SR is set and the Output Level Figure 20. Output Compare Timing Diagram INTERNAL CPU CLOCK bit (OLVL1) of the TCR is clocked to the OCMP1 pin (see output compare timing diagram). OLVL1 is copied to the corresponding output level latch and hence, to the OCMP1 pin regardless of whether the Output Compare Flag (OCF1) is set or not. The value in the OCR1 and the OLVL1 bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed time-out. An interrupt follows a successful output compare if the corresponding interrupt enable bit OCIE of the TCR is set, provided the I-bit of the CCR is cleared. Otherwise, the interrupt remains pending until both conditions are true. It is cleared by reading the SR, followed by accessing the LSB of the OCR1. After a processor write cycle to the OCHR1 register, the output compare function is inhibited until the OCLR1 is also written. Thus, the user must write both bytes if the MSB is written first. A write made only to the LSB will not inhibit the compare function. The minimum time between two successive edges on the OCMP1 pin is a function of the software program. T10 INTERNAL TIMER CLOCK T11 COUNTER FFFCh FFFDh FFFEh FFFFh 0000h COMPARE REGISTER CPU WRITES FFFFh FFFFh (Note 1) COMPARE REGISTER LATCH OUTPUT COMP. FLAG OCF AND OCMP PIN VR000B94 38/119 38 ST7272 16-BIT TIMER (Cont'd) The OCMP1 output latch is forced low during reset and stays low until valid compares change it to a high level. Because the OCF1 flag and the OCR1 are undetermined at power-on and are not affected by an external reset, care must be exercised when initiating the output compare function by software. The following procedure is recommended to prevent the OCF1 flag from being set between the time it is read and the subsequent write to OCR1: Write to OCHR1 (further compares are inhibited). Read the SR (first step of the clearance of OCF1 [it may be already set]). Write to OCLR1 (enables the output compare function and clears OCF1). Output Compare Register 2 The Output Compare Register 2 (OCR2) is a 16-bit register, which consists of two 8-bit registers: the most significant byte register (OCHR2) at address 001Eh and the least significant byte register (OCLR2) at address 001Fh. This register operates in a similar fashion to Output Compare Register 1. For a complete description, please refer to the latter and substitute the appropriate suffix in the bit and register names. Software Forced Compare The main purpose of the forced compare function is to facilitate fixed frequency generation. When the Force Output Level 1 bit (FOLV1) of TCR is written to 1, OLVL1 is copied to pin OCMP1 or TX pin (if TXEN control bit is set). To provide this function, internal logic allows a single instruction to change OLVL1 and causes a forced compare with the new value of OLVL1. OCF1 is not affected and thus, no interrupt request is generated. 4.3.6 Register Description (CR) TIMER CONTROL REGISTER (0012 h) Read/Write Reset Value: 0000 00x0 (00h or 02h) 7 ICIE OCIE TOIE RES FOLV1 RES IEDG1 0 OLVL1 er the OCF1/2 status flags of SR are set. If the OCIE bit is cleared, the interrupt is inhibited. b5 = TOIE: Timer Overflow Interrupt Enable If TOIE is set, a timer interrupt is enable whenever the TOF status flag of SR is set. If the TOIE bit is cleared, the interrupt is inhibited. b4 = Reserved, Read as '0' b3 = FOLV1: Force Output Compare 1. When written to 1, FOLV1 forces OLVL1 to be copied to the OCMP pin. b2 = Reserved, Read as '0' b1 = IEDG1: Input Edge 1 The value of the IEDG1 bit determines which level transition on IC_A input will trigger a free running counter transfer to the ICR1. When IEDG1 is high, a rising edge triggers the capture and when low, a falling edge does. b0 = OLVL1: Output Level 1 The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs at OCR1. (SR) TIMER STATUS REGISTER (0013 h) Read Only Reset Value: Undefined 7 ICF1 OCF1 TOF ICF2, OCF2 0 0 0 0 b7 = ICF1 Input Capture Flag 1 ICF1 is set when a proper edge has been sensed by the input capture edge detector at IC_A. The edge is selected by the IEDG1-bit in TCR. ICF1 is cleared by a processor access to the SR while ICF1 is set followed by an access (read or write) to the low byte of ICR1 (ICLR1). b6 = OCF1 Output Compare Flag 1 OCF1 is set when the content of the free running counter matches the content of OCR1. It is cleared by a processor access to SR while OCF1 is set followed by an access (read or write) to the low byte of OCR1. b5 = TOF Timer Overflow TOF is set by a transition of the free running counter from FFFFh to 0000h. It is cleared by a processor access to SR while TOF is set followed by an access (read or write) to the low byte of the counter low register. TOF is not affected by an access to the Alternate Counter Register. 39/119 b7 = ICIE: Input Capture Interrupt Enable If ICIE is set, a timer interrupt is enabled whenever the ICF1/2 status flags of SR are set. If the ICIE bit is cleared, the interrupt is inhibited. b6 = OCIE: Output Compare Interrupt Enable If OCIE is set, a timer interrupt is enabled whenev- 39 ST7272 16-BIT TIMER (Cont'd) b4 = ICF2 Input Capture Flag 2 ICF2 is set when a negative edge has been sensed by the input capture edge detector at IC_B. ICF2 is cleared by a processor access to the SR while ICF2 is set followed by an access (read or write) to the low byte of ICR2 (ICLR2). b3 = OCF2 Output Compare Flag 2 OCF2 is set when the content of the free running counter matches the content of OCR2. It is cleared by a processor access to SR while OCF2 is set followed by an access (read or write) to the low byte of OCR2. b2-0 = Unused, read as '0'. INPUT CAPTURE REGISTER 1 (IC1HR) High Byte address 0014 h -- Reset Value: Undefined 7 MSB 0 LSB 7 MSB 0 LSB High byte address 0018 h -- Read Only Reset Value: 1111 1111 (FF h) 7 MSB 0 LSB COUNTER REGISTER (CNTLR) Low byte address 0019 h -- Read/Write Read Only Reset Value: 1111 1100 (FC h) 7 MSB 0 LSB INPUT CAPTURE REGISTER 1 (IC1LR) Low byte address 0015 h Reset Value: Undefined 7 MSB 0 LSB Writing to this Register will cause the counter to be reset to its reset value of FFFCh. Flags and enable bits remain unaltered by this operation. -- Read Only ALTERNATE COUNTER REGISTER (ACNTHR) High byte address 001A h -- Read Only ) Reset Value: 1111 1111 (FF h 7 MSB 0 LSB OUTPUT COMPARE REGISTER 1 (OC1HR) High byte address 0016 h -- Reset Value: Undefined 7 MSB 0 LSB Read/Write ALTERNATE COUNTER REGISTER (ACNTLR) Low byte address 001B h -- Read/Write ) Reset Value: 1111 1100 (FC h 7 0 LSB OUTPUT COMPARE REGISTER 1 (OC1LR) Low byte address 0017 h Reset Value: Undefined COUNTER REGISTER (CNTHR) 40/119 MSB -- Read/Write Writing to this Register will cause the counter to be reset to its reset value of FFFCh. Flags and enable bits remain unaltered by this operation. 40 ST7272 16-BIT TIMER (Cont'd) INPUT CAPTURE REGISTER 2 (IC2HR) High byte address 001C h -- Read Only Reset Value: Undefined 7 MSB 0 LSB OUTPUT COMPARE REGISTER 2(OC2HR) High byte address 001E h -- Reset Value: Undefined 7 MSB 0 LSB Read/Write INPUT CAPTURE REGISTER 2(IC2LR) Low byte address 001D h -- Reset Value: Undefined 7 MSB 0 LSB OUTPUT COMPARE REGISTER 2 (OC2LR) Low byte address 001F h Reset Value: Undefined 7 MSB 0 LSB Read Only -- Read/Write 41/119 41 ST7272 4.4 SYNC PROCESSOR (SYNC) 4.4.1 Introduction The Sync Processor manages the video synchronization signals, and is used in conjunction with the Timer to provide information and status on the video standard and timings. This Sync Processor is a superset of the ST7271 sync processor. In order to be able to resolve all required timing information, the MCU must operate with an oscillator frequency of 8MHz. Separate Horizontal and Vertical Synchronization pulses, provided on the (HSYNCI1, VSYNCI1) or (HSYNCI2, VSYNCI2) pins, are accepted, and polarity is detected by hardware. In this case HSYNCO = HSYNCI (with programmable polarity inversion, but without blanking). Alternatively a composite sync signal (sync pulses only) may be input on CSYNCI (or HSYNCI pin), with automatic synchronization pulse extraction and hardware polarity detection. Extraction of VSYNCO may be obtained from a composite signal (OR, XOR, or serration pulses). Note: if the input is a composite signal both VSYNCO and HSYNCO will be extracted (the latter can be blanked during the VSYNCO pulse as far as potential serration pulses are concerned). Processed sync pulses may be output to external parts of the circuit through the HSYNCO and VSYNCO pins, with programmable polarity. An independent programmable duration/polarity backporch or pseudo front-porch (clamping) output signal (CLMPO) generator can be used as a Video clamp reference signal for the Video Preamplifier IC. Where HSYNCO and VSYNCO are extracted from CSYNCI, the signal is always suppressed during vertical blanking. 4.4.2 Features - Determination H Sync In1 and V Sync In 1 signal levels - Sync detection of H Sync In, V Sync In, C Sync In, H Fly In, V Fly In signals - Detection of H Sync In polarity and presence of Composite Sync - V Sync Out Polarity detection - Programmable Clamp Out pulse polarity - Built-in composite video blanking signal generator - Internal programmable H Sync Out/V Sync Out frequency generator 42/119 - Acquisition of the number of scan lines during one frame - Acquisition of the delay between two HSync pulses - Detection of Pre-equalization pulses - Programmable inhibition of Pre equalization/Post equalization pulses - Programmable V Sync Out pulse width extension - One shot programmable H sync edge generator - Programmable V Sync Out pulse width extension during detection of post-equalization pulses - VSYNCI1 Schmitt trigger sync signal is DDC1 clock reference for DDC/DMA cell. 4.4.3 Functional Description The main function of the Sync Processor can be summarized as consisting of the following tasks: - Checking the presence of input signals by H/W (VSYNCI, HSYNCI and CSYNCI) - Polarity Detection by H/W (VSYNCI, HSYNCI or CSYNCI) - HSYNCO, VSYNCO Extraction or Self Generation - Video Standard Discrimination - Composite Video Blanking Generator Stage These tasks are performed by the Sync Processor in close conjunction with the Timer Input captures, and user software. The block diagram of the Sync Processor is shown in Figure 22. This also shows the internal connections to the Timer Input Capture A (IC_A) and Input Capture B (IC_B). All quoted timings are for operation at 8MHz oscillator frequency. 4.4.3.1 Checking the presence of input signals The Sync Processor offers two techniques for checking signal presence, a S/W regular check and an indirect check which is interrupt driven and uses the H/W of the Sync Processor. Direct Check Using the Latch Register (LATR), it is possible to detect the presence of HSYNCI, VSYNCI, CSYNCI, HFly and VFly signals. These latches are set upon falling edge detection, and cleared by S/W. With the Timer Overflow or Output Compare timebase, the Mode Recognition and Power Management tasks can be easily made. 42 ST7272 SYNC PROCESSOR (Cont'd) Indirect Check To use the indirect check method, multiplexers are set to connect the VSYNCI input to Timer Input Capture A and HSYNCI or CSYNCI to the Input Capture B. Step I - Checking VSYNCI. Any interrupt request coming from IC_A is monitored. (On detecting VSYNCI, the software may either detect the VSYNCI polarity or check for the presence of HSYNCI). Step II - Checking HSYNCI. The HSYNCI input is connected directly to IC_B. An interrupt request is waited for (on detecting HSYNCI, the software may either detect the HSYNCI polarity or check the CSYNCI presence). Step III - Checking CSYNCI. The CSYNCI input is connected directly to IC_B. An interrupt request is waited for. Note. Input Capture A edge detection polarity can be selected to be positive or negative. Input Capture B edge detection polarity is fixed for negative edges. Steps I-III may be carried out in parallel. Figure 21. Simplified Schematic of Video Blanking Stage To Edge detector (LATR) PC0/HFBACK To Edge detector (LATR) R PB0/VFBACK S BLKEN PA7/BLK PD2/VSYNCO HFBACK, VFBACK and VSYNCO signals should have positive polarity 43/119 43 ST7272 SYNC PROCESSOR (Cont'd) 4.4.3.2 Polarity Detection The Sync Processor also offers two techniques for checking the polarity of signals: a regular software direct check and an indirect check which uses the Sync Processor hardware, thus avoiding CPU intensive S/W polling. Indirect Polarity Detection This method involves the internal 5-bit up/down counter. At the beginning of the detection phase, '11111' is written into the CCR register (CVM bits). These bits are refreshed by the 5-bit counter value at every detected edge on the signal considered. The counter increments when the signal is high; otherwise it decrements. Figure 22. Sync Processor Block Diagram Software can thus check the SYNC Processor capture register after an interrupt (with the signal connected to IC_A or IC_B), or by polling. In the case of positive polarity the capture value will be '00000', since the counter stays at this value after underflowing. Otherwise, it will be non-zero (the value depending on the resolution of the counter) and thus indicate that the signal is of negative polarity. This one-shot detection approach covers separate HSYNCI and VSYNCI signals only. For composite input signals, the software simply needs to check that the VSYNCO period and polarity are stable. VSYNCI1 VSYNCI2 0 1 Latch Pulse Detect Vsynci LCV1 Vsync* IC_A TIMER V SyncO Polarity LCV1 Polarity Detector 0 V Sync Correction 1 VSYNCO SYNOP HVGEN HVSEL Capture LD Register Control Logic V S Y N C O Sync & Edge Detect LCV0 Up / Down EN 5-Bit Counter CLK fINT Latch Latch 00 1F match match IC_B TIMER H-Inhibit ON/OFF Sync Generator Sync Analyser Sync Corrector H/W Block VSYNC +Generator 40 - 120Hz Dutycyclerange 40 -120 us HSYNC +Generator 30 -80 kHz Duty cycle range 5 -25 % Prescaler Latch HVSEL PulseDetect 0 0 1 1 SCI0 Latch Pulse Detect PSCD HSYNCI1 HSYNCI2 CSYNCI /SOG HSYNCI / CSYNCI SYNOP H SyncO Polarity 1 HSYNCO Back Porch Clamp Generator SCI1 Clamp Polarity CLPINV1 VR02071A H SyncO Correction these Pinscanbereadandwrittento 0 CLMPO HVGEN these Pinscanbe read 44/119 44 ST7272 SYNC PROCESSOR (Cont'd) Direct Polarity detection HSYNCI/CSYNCI polarity detection makes use of the UPLAT and DOWNLAT latches connected to the 5 bit Up/Down counter. This pair of latches in LATR indicates the nature of the HSYNCI Sync signal: UPLAT 0 0 1 1 DWNLAT 0 1 0 1 H Sync In Nature No Info Negative Sync Positive Sync Composite Sync The VSYNCI polarity detection is done by H/W and returned in the VPOL bit of the POLR register. The delay between VSYNC polarity changes and the VPOL bit typically toggles within 4 msec. The polarity detector includes an integrator to filter possible incoming VSYNC glitches. Figure 23. Horizontal Sync Input Timing or: Hor. total time: min. 8.33 s, max. 66.66 s (120kHz) (15kHz) VR01961 Sync. pulse width: min. 750ns, max. 7 s Figure 24. Vertical Sync Input Timing or: Ver. total time: min. 5ms, max. 25ms (200Hz) (40Hz) VR01961A Sync. pulse width: min. 0.0384ms, max. 0.600ms 45/119 45 ST7272 SYNC PROCESSOR (Cont'd) 4.4.3.3 VSYNCO Extraction VSYNCO is extracted from CSYNCI with the aid of the 5-bit up/down counter. Initially, the width of a Horizontal sync component pulse is determined automatically by hardware, which defines a threshold for the counter (which may be replaced with an optional user-defined value including a tolerance factor). The circuit then checks for any input period greater than this captured value. This is then processed as for the VSYNCO signal. The S/W should first select the acquisition mode to measure the internal Horizontal sync component pulse width. The time-equivalent value is read after this value is captured in the CCR register. If a user-defined tolerance is to be added, an updated value can be re-written into the register. Capture occurrence can be flagged by the timer Input Capture interrupt or by reading a new value in the Sync Processor Control Register. After this step, the S/W should set the extraction mode (LCV1 bit) to start the VSYNCO sync extraction by H/W as described in the following paragraph, for a negative polarity signal. In extraction mode, the 5-bit comparator checks the counter value with respect to the threshold. When the counter reaches the threshold on a downcount, VSYNCO is asserted. During the vertical blanking period, the counter value is decreased down to a programmable minimum, i.e. it does not underflow. When the vertical period is over, the counter starts counting up, and when the maximum count is reached, VSYNCO is negated. The extracted signal may be validated by S/W since it is input to Timer IC_A. The threshold is greater than the count for a HSYNCI pulse. Serration pulses during vertical blanking can be filtered. Similarly, positive CSYNCI signals are covered by properly selecting the edge sensitivity on the Hsync width measurement mode (LCV0 bit). Figure 25. VSYNCO Generation for Negative Polarity Composite signals, showing Serration pulses Counter Input Counter value: Max Threshold Min V-sync generated Threshold reached HSYNCO VR01990 Max reached 46/119 46 ST7272 SYNC PROCESSOR (Cont'd) 4.4.3.4 Standard Discrimination Discrimination of video standards is supported by use of the Timer peripheral in conjunction with the Sync Processor. For this purpose, either HSYNCI or CSYNCI is prescaled by 256. Note: The prescaler can be bypassed for frequency synchronization signals lower than specified. The prescaler can be reset (disabled/enabled) to synchronize the H Sync period measurement with V Sync. This function is carried out by using the Timer Input-Capture Channels: a) VSYNCI is directly connected to IC_A (after synchronization; PV measured). b) HSYNCI or CSYNCI is prescaled (or not) by a factor of 256 in the Sync Processor, and then sent to IC_B. (PHx256 measured). Signal timing can be directly calculated using the time values between the appropriate interrupts generated by the Timer, and then used for comparison against existing pre-defined standards. An averaging method on Period measurement can yield more accurate timing for comparison, if serration pulses are present on CSYNCI. Application Note: Forcing video blanking by S/W, by forcing the PA7 output low (Data Register bit) will do the job without any electrical conflicts, due to the open-drain feature of the PA7 I/O pin. If the VFBACK signal disappears, the video blanking output signal will remain permanently low due to the RS flip/flop. If PA7 is set as a digital input and the blanking output is enabled, the PA7 Data Register bit will indicate the BLK signal level. If this block is not used, PC0 and PB0 can be used as falling edge signal detectors (LATR). 4.4.3.6 Inputs The Sync Processor inputs consist of the Video Synchronization strobe pulses: - VSYNCI1, VSYNCI2 (Vertical Sync input, TTL Level, Schmitt triggered). - HSYNCI1, HSYNCI2 (Horizontal Sync input, TTL Level, Schmitt triggered). - CSYNCI (Composite Sync input, TTL Level, Schmitt triggered). Note: The Composite Sync signal may also be received on the HSYNCI input if this is supplied by the external circuit and the I/O function of the CYSYNCI I/O pin for is required. Selection of the Sync input sources (HSYNCI1, VSYNCI1 or HSYNCI2 (PC1), VSYNCI2 (PD4)) is accomplished via the HVSEL bit of the MISCR. Input Signal Waveforms. The input signals must contain only synchronization pulses. Timing characteristics of HSYNCI and VSYNCI: - Where serration pulses are present on CSYNCI/HSYNCI, these pulses should be externally generated with a minimum of half a line delay from the VSYNCI edge. - The HSYNCI or CSYNCI signal, optionally prescaled by 256, is connected to the IC_B input (Timer Input Capture B) of the Timer. - The Timer resolution is 500ns for an external oscillator frequency of 8MHz. 4.4.3.7 Outputs Application Note: To use the video blanking signal, the BLKEN bit must be set, PC0 and PB0 must be configured as digital inputs, and PA7/BLK as either a digital input or as a digital output set to a logic high level. HSYNCO: HSYNC Output, (CMOS Level). This programmable polarity signal can be blanked by S/W during the vertical period (if the input is a composite signal). Its internal propagation delay has been optimized to its lowest possible delay. 47/119 Accuracy of period measurement Basically, the substraction between two consecutive Input Captures (16-bit value) gives the period for 256xPH (horizontal period), and PV (vertical period). The period accuracy is one Timer clock (500ns), so that the tolerance is: 256xPH tolerance: 500ns (1.95 ns for PH itself) PV tolerance: 500 ns 4.4.3.5 Video Blanking Signal Generator This block involves VSYNCO, HFBACK and VFBACK as input signals and BLK Out as Video Blanking Output signal (active low). The Video Blanking output (BLK) can be enabled/disabled by S/W. This pin is a 12V open-drain output and can be AND-wired with any external video blanking signa (coming, for example, from the TDA9103 Deflection processor). 47 ST7272 SYNC PROCESSOR (Cont'd) If separate HSYNCI and VSYNCI signals are provided, no blanking is generated on HSYNCO. VSYNCO: VSYNC Output, (CMOS Level) with programmable polarity. VSYNCO is connected to IC_A, input to Timer Input Capture A. CLMPO: (CMOS level) back-porch clamp signal with programmable polarity. If VSYNCO is extracted from a composite signal, the minimum delay is 500ns + HSYNCO pulse width. The maximum delay is software defined (the threshold value in extraction mode) and corresponds to 8750 ns. Notes: - If separated HSYNCI and VSYNCI are provided, no blanking is generated on HSYNCO. - No direct interrupt request is used by the Sync Processor, although the optional interrupt in the Figure 26. Back Porch (CLMPO) Delay timer can be used by the software since VSYNCO and HSYNCI/CSYNCI signals are connected to Input Capture (IC_A and IC_B, respectively). - The Timer Interrupt Request should be masked during a write access to the SYNC Control Registers. Application note: The clamping pulse generator can also be configured as a pseudo front-porch pulse generator instead of back-porch signal by sensing the leading edge of the H Sync O signal. If the clamping pulse generator block is not used (e.g. when the TDA920X Video Preamplifier with internal clamping pulse generator is used), the output pin can be used as normal I/O. HSYNCO: Maximum delay is 250ns CLMPO: Programmable back porch clamping width (0; 250ns; 500ns; 1 s) VR01961B Note: The Clamping pulse generator can generate both back porch and pseudo front porch signals and polarity can be programmed as positive or negative. The illustration above shows the maximum delay between the trailing edge of HSYNCO and the leading edge of CLMPO for a back porch signal; the delay (250 ns max) will be the same in the case of a pseudo front porch signal, but in this case the delay will be between the leading edge of HSYNCO and the leading edge of CLMPO. Note that the clamping signal pulse width can be programmed as 0, 250ns, 500ns or 1 via bits BP0 and BP1 of the MCR register. s 48/119 48 ST7272 SYNC PROCESSOR (Cont'd) 4.4.4 Register Description (CCR) COUNTERCONTROL REGISTER (0042 h) Read/Write Reset Value 0000 0000 (00 h) 7 PSCD LCV1 LCV0 CV4 CV3 CV2 CV1 0 CV0 (MCR) MUX CONTROL REGISTER (0041 h) Read/Write Reset Value: 0000 0000 (00 h) 7 BP1 BP0 SCI1 SCI0 HS1 HS0 VOP 0 VIP b7 = PSCD: Prescaler Enable bit PSCD 0 1 Enable/Disable the 256 Prescaler Prescaler enabled Prescaler disabled and preset to FEh b7-6 = BP1, BP0: Back Porch Pulse Width control BP1 0 0 1 1 BP0 0 1 0 1 Back Porch pulse width No Back Porch 250ns 500ns 1000ns Application note: For a Composite Sync signal, the horizontal period measurement can be synchronized on VSYNC pulse by doing a Set/Reset of PSCD bit by S/W during VICAP interrupt. b6-5 = LCV1,LCV0: VSYNCO Extraction Control Bits b4-0 = CV4-0: Counter Captured Value. These bits correspond to the counter captured value in different modes. Upon VSYNCO extraction, it corresponds to a HSYNCI pulse-width measurement, which may be changed by software before extraction. LCV1 0 LCV0 0 VSYNC0 Control Bits Acquisition mode Counter capture on input signal falling edge Acquisition mode Counter capture on input signal rising edge Extraction mode CSYNCI/HSYNCI Negative polarity CV4-0 = counter minimum threshold Extraction mode CSYNCI/HSYNCI Positive polarity CV4-0 = counter maximum threshold b5 = SCI1: Horizontal/Vertical Signal Path Selection Bit. This bit selects the path for the incoming signals towards IC_A, IC_B, VSYNCO and HSYNCO: SCI1 0 5 bit Up/Down Counter Mode Selection VSYNCI Polarity Detection IC_B connected to HSYNCI/CSYNCI w/o prescaling HSYNCI/CSYNCI Polarity detection / VSYNCO Extraction IC_B connected to Prescaled HSYNCI/CSYNCI 1 Application Note: This bit should be always set b4 = SCI0: HSYNCI/CSYNCI Selection SCI0 0 1 HSYNCI/CSYNCI Sync Processor Input selection HSYNCI selected CSYNCI selected 0 1 1 0 1 1 49/119 49 ST7272 SYNC PROCESSOR (Cont'd) b3-2 = HS1, HS0: Horizontal Signal Selection Bits. These bits allow inversion of the HSYNCI/CSYNCI polarity, output as HSYNCO, as well as the generation of CLMPO as follows: HS1 0 0 1 1 HS0 0 1 0 1 HSYNC Selection Mode CLMPO after HSYNCO rising edge HSYNC0 <- (HSYNCI, CSYNCI) CLMPO after HSYNCOI rising edge HSYNC0 <- (HSYNCI, CSYNCI) CLMPO after HSYNCOI falling edge HSYNC0 <- (HSYNCI, CSYNCI) CLMPO after HSYNCOI falling edge HSYNC0 <- (HSYNCI,CSYNCI) (CFGR) CONFIGURATION REGISTER (0040 h) Read Write Reset Value: 0000 0000 (00 h) 7 HACQ VACQ XTRAH 2FHINH VEXT Q'2 Q'1 0 Q'0 bit 7: HACQuisition (set by S/W, cleared by H/W when the acquisition is over) HACQ 0 1 Horizontal Sync Acquisition Mode (HVGEN=0) Acquisition is over, and the result can be read in HGENR Measurement of Low level period of HSYNC activated b1-0 = VOP,VIP: Vertical Signal Polarity Selection Bits. These bits are only S/W controlled and are related to the polarity of the outgoing vertical signal. VOP 0 0 1 1 VIP 0 1 0 1 VSYNC Selection Mode ICAP_A <- VSYNCI VSYNCO <- VSYNCI ICAP_A <- VSYNCI VSYNCO <- VSYNCI ICAP_A <- VSYNCI VSYNCO <- VSYNCI ICAP_A <- VSYNCI VSYNCO <- VSYNCI bit 6: VACQuisition (Set by S/W, cleared by H/W when the acquisition is over) VACQ 0 1 Vertical Sync Acquisition Mode (HVGEN=0) Acquisition is over, and the result can be read in VGENR Measurement of the number of scan lines during VSYNCO low level period is activated Application Note: VIP bit should be always fixed to "0". VOP bit is used to negate or not the VSYNCO sync signal. In composite sync extraction mode (LCV1=1), the internal extracted VSYNC is ALWAYS negative polarity. If each vertical input capture the VPOL bit is copied by S/W on VOP bit, the VSYNCO sync signal will have constant positive polarity. bit 5: XTRAH (HVGEN=0, HACQ=0) HSYNC edge generation enable. This function can correct HSYNC especially in composite sync where a HSYNC pulse is missing just before VSYNC pulse. This function generates an HSYNC raising edge when the monostable reaches 00, once per frame. 1 = Function enabled/ 0 = Function disabled. bit 4: 2FHINH (HVGEN=0, HACQ=0) Inhibition of Pre/Post equalization pulses. This function can remove pre/post equalization pulses on HSyncO signal. The duration of the inhibition is done between the falling edge of H Sync O up to the monostable reaches 8 value. (HGENR-2us) 1 = Function enabled / 0 = Function disabled. bit 3: VEXT (HVGEN=0, VACQ=0, HACQ=0) V Sync Out pulse width extension. This function allows a VSYNCO pulse width extension in case of post-equalization pulse presence (2FHDET signal), up to 7 scan lines. 1 = Function enabled (extension done after the VGENR extension) 0 = Function disabled Note: If VGENR=00, this function is disabled. bit 2.0: Q'2..Q'0 These are the read/write less significant bits of the VGENR 11-bit counter. 50/119 50 ST7272 SYNC PROCESSOR (Cont'd) (LATR) LATCH REGISTER (0044 h) Read/Write Reset Value: 0000 0000 (00 h) 7 CSYN HSYN VSYN HFLY VFLY UPLAT DWNLAT HFLY/VFLY may be used for the DDC/Access Bus Self-Test command. 2FHLAT may be used to detect pre/post-equalization pulses or an excessively high Horizontal Frequency. (POLR) POLARITY REGISTER (0043 h) 0 2FHLAT b0= 2FHLAT - Set when Pre/Post equalization pulses are detected cleared by S/W (write of zero) (valid if HVGEN=0, HACQ=0) b1= DWNLAT - Set when the 5 bit up-down counter reaches its minimum value (00 or Threshold) Cleared by S/W. b2= UPLAT - Set when the 5 bit up-down counter reaches its maximum value (1F or Threshold) Cleared by S/W. b3 = VFLY - Set on falling edge of VFLY/PB0 input. Cleared by S/W. b4 = HFLY - Set on falling edge of HFLY/PC0 input Cleared by S/W. b5 = VSYN - Set on falling edge of VSyncIn. Cleared by S/W. b6 = HSYN - Same for HSync In (after HVSEL mux). Cleared by S/W. b7 = CSYN - Set on falling edge of CSyncIn. Cleared by S/W. Application Note: DWNLAT and UPLAT may be used for HSYNC polarity detection and Composite Sync detection. CSYN/HSYN/VSYN may simplify the mode recognition and Power Management features. Read only 4 MSB bits Read/Write 4 LSB bits Reset Value: 0000 0000 (00 h) 7 ---0 VPOL 2FHDet 0 0 CLPINV 0 0 bit 0: 0 - Not used bit 1: CLPINV - Programmable Clamp Out pulse polarity (0: Positive, 1: Negative) bits 2,3: 0 - RESERVED bit 4: 2FHDet - Detection of Pre/Post equalization pulses (Read Only) (HVGEN = 0, HACQ = 0) bit 5: VPOL - Vertical sync polarity (Read Only) (0: Positive, 1: Negative) VSYNC: [40..200] Hz, Pulse width [10..700] us bit 6: 0 - RESERVED bit 7: X - UNDEFINED Application Note: If the Vertical Sync polarity is changing, the VPOL bit should be updated after a typical delay of 4 msec. 51/119 51 ST7272 SYNC PROCESSOR (Cont'd) (HGENR) HORIZONTAL SYNC GENERATOR REGISTER (0045 h) Read/Write Reset Value: 0000 0000 (00 h) 7 MSB 0 7 LSB MSB LSB 0 (VGENR) VERTICAL SYNC GENERATOR REGISTER (0046 h) Read/Write Reset Value: 0000 0000 (00 h) Case HVGEN = 1: Generation mode This register programs the H Sync generated frequency when HVGEN=1 The generated signal (Positive polarity) is as follows: Pulse width: 2 us. Period: (HGENR/4) us. Note: HGENR value must be in [8..255] range. Case HVGEN = 0: Acquisition/Correction Mode (HSYNCO/VSYNCO must be positive sync signals) Sub-case HACQ = 1: Acquisition Mode By setting HACQ bit by S/W the acquisition mode starts When HACQ is cleared by H/W, HGENR returns the duration of HSYNCO low level. The acquisition should be done before the correction mode. Sub-case HACQ = 0: Correction Mode In this mode, the final HSYNCO signal on the pin can be corrected in order to detect and inhibit pre/post equalization pulses, etc... See dedicated control bits for more information HGENR (hex value) 1F 3F 7F FF HGENR (hex value) 1F 1F 3F 3F 7F 7F H Period (s) 8 16 32 64 H Freq (KHz) 125 62.5 31.25 15.6 HPeriod (s) 8 8 16 16 32 32 Pulse width (s) 2 2 2 2 H Freq (KHz) 125 125 62.5 62.5 31.25 31.25 Duty Cycle 25% 12.5% 6.2% 3.1% Case HVGEN = 1: Generation mode This register programs the V Sync Generated signal frequency (11 bit value) Pulse width: 4 HGEN periods Period: (HGENR*8) scan lines. VGENR value must be in [5..255] range. This block works as an 11 bit Horizontal line counter (2047 scan lines per frame max) Note that the 3 less significant bit are accessible in CFGR register. If you want to have a vertical period multiple of 8*HGENR, the 3 LSB (in CFGR) must be freeze to 000. Case HVGEN = 0: Acquisition/Correction Mode (HSYNCO and VSYNCO must be positive sync signal) Sub-case VACQ = 1: Acquisition Mode By setting VACQ bit by S/W the acquisition mode starts When VACQ is cleared by H/W, VGENR returns the number of scan lines during VSYNCO low level period Sub-case VACQ = 0: Correction Mode VSYNCO pulse width is extended of VGENR scan lines. If VGENR = 0, all VSYNCO corrections are disabled. (except 2FHEN test control bit) VGENR (hex value) 7FF (2047) 400 (1024) 7FF (2047) 400 (1024) 7FF (2047) 400 (1024) V Period (ms) 16.3 8.2 32.6 16.4 130.5 32.8 V Freq (Hz) 61 122 30.6 60.9 15 30 Pulse width (s) 32 32 64 64 128 128 52/119 52 ST7272 SYNC PROCESSOR (Cont'd) (ENR) ENABLE REGISTER (0047 h) Read/Write Reset Value: 0000 0000 (00 h) 7 HSyncIn 1 0 VSyncIn 1 bit 4 = HVGEN enable the Sync Generation function) HVGEN 0 1 Generation/Acquisition/Correction mode Selection Acquisition/Correction Mode H/V Sync Generation 0 0 BLKEN HVGEN 2FHEN HINH bit 0 = VSYNCIN1 (Read Only): Returns the VSYNCIN1 pin level bit 1 = HSYNCIN1 (Read Only): Returns the HSYNCIN1 pin level bit 2: HINH - HSYNCO Blanking HINH 0 1 H SYNCO blanked by extracted VSYNCO HSYNCO blanked HSYNCO not blanked (=HSYNCI) bit 5 = BLKEN - Blanking Output Enable BLKEN 0 1 Enable/Disable Video Blanking Signal Generation Function disabled Function enabled bit 6..7: 0 - Reserved Application Note: HSYNCIN1 and VSYNCIN1 may simplify the Power Management Algorithm. After the ST7271 compatible Sync Processor Block, a new H/W cell has been pipelined in order to improve the functionality with optimized H/W. This block works in 3 different modes which are: Generation of Sync Signals, Analysis of the Sync Processor Output signals, and correction of sync signals if necessary. Overview of generation/acquisition/correction H/W block functionality: bit 3 = 2FHEN - VSYNCO expansion (HVGEN=0, HACQ=0, VACQ=0) 2FHEN 0 1 VSYNCO Forced high when detection of 2FH pulses Function disabled (Normal Application configuration) Function enabled: VSYNCO = VSYNCO + 2FHDET 53/119 53 ST7272 SYNC PROCESSOR (Cont'd) Table 12. Summary of most important Sync Processor Modes Sync Processor Mode DSUB Selected as Inputs (HSYNCI1/VSYNCI1) BNC Selected as Inputs (HSYNCI2/VSYNCI2) Don't drive the monitor with any sync signals Generate Sync Signals to drive the Monitor H/W Use the Sync Processor to drive the monitor H/W by incoming sync signals Analyse the number of Scan Lines during one vertical frame Analyse the HSYNC delay between two pulses SYNOP ----0 1 1 ----HVSEL 0 1 ---------HVGEN ------1 0 0 0 HACQ ------0 ----1 VACQ ------0 --1 --- Table 13. Sync Generator/Analyzer/Corrector H/W Block Description Function Application s Drive the monitor H/W when no or bad sync signals are received Sync Generation Allow stabilised OSD screen when monitor is unlocked Smooth frequency transitions Faster auto alignment system for Factory or Service Purpose Fast estimation of the incoming H Sync Input period Sync Acquisition Estimation of the number of scan lines per frame Simplify the OSD vertical centring algorithm Detection of pre/post equalisation pulses Detection of H SYNC reaches too high frequency Inhibition of Pre/Post equalisation pulses Sync Correction Programmable VSYNCO pulse width extension (PLL Inhibit) Possible VSYNCO extra pulse width extension during post-equalisation pulses detection up to XX lines) Possible generation of VSYNCO sync upon detection of high frequency H Sync Pulses Possible generation of missing H Sync Edge in composite sync 54/119 54 ST7272 4.5 DIGITAL TO ANALOG CONVERTER 4.5.1 Introduction The ST7272 offers two types of Digital to Analog Converter, with differing step resolutions based on the Pulse-Width Modulator (PWM) and Binary Rate Multiplier (BRM) Generator technique. These may act as digital potentiometers, when used with external, filtering to control brightness, saturation/contrast and other analog variables. A 10-Bit PWM/BRM with a repetition rate of 64KHz, 250ns resolution and a step of 5mV (0/5V, excepting DA2). 16 channels are provided with this configuration (channels PWM2-PWM17 with outputs DA2-DA17 respectively). DA2 has a fixed open-drain output, with an external V capability DD up to 12V, while DA3-DA17 are programmable to open-drain or push-pull output configuration, with a 0-VDD (+5V) range. A 12-bit PWM/BRM generator (2 Channels: PWM0 and PWM1) with a repetition rate of 64KHz, 250ns resolution and a step of 1.25mV (0/5V excepting DA0). The channels PWM0 and PWM1 correspond with outputs DA0 and DA1 respectively. DA0 has a fixed open-drain output, with an external VDD capability up to 12V, while DA1 is programmable to open-drain or push-pull output configuration, with a 0-VDD (+5V) range. 4.5.2 Functional Description 4.5.2.1 10-bit PWM/BRM The 10-Bits of the 10 bit PWM/BRM are distributed as 6 PWM bits and 4 BRM bits. The generator conFigure 27. PWM Generation COUNTER OVERFLOW 63 COMPARE VALUE OVERFLOW OVERFLOW sists of a 10-bit counter (common for all channels), a comparator and the PWM/BRM generation logic. PWM Generation The counter increments continuously, clocked at the main oscillator frequency divided by 2 (with a period tCLK = 1/fCLK = 250ns). Whenever the 6 least significant bits of the counter (defined as the PWM counter) overflow, the output level for all active channels is set. The state of the PWM counter is continuously compared to the PWM binary weight for each channel, as defined in the relevant PWM register, and when a match occurs the output level for that channel is reset. This Pulse Width modulated signal must be filtered, using an external RC network placed as close as possible to the associated pin. This provides an analog voltage proportional to the average charge passed to the external capacitor. Thus for a higher mark/space ratio (High time much greater than Low time) the average output voltage is higher. The external components of the RC network should be selected for the filtering level required for control of the system variable. Each output may individually have its polarity inverted by software, and can also be used as a logical output. 000 t PWM OUTPUT 16 s (62.5kHz) t VR01954 55/119 55 ST7272 DIGITAL TO ANALOG CONVERTER ( ont'd) C Figure 28. Typical PWM Output Filter 1k PWM OUT C VR01955 C (mF) 0.256 2.56 V RIPPLE (mV) 78 7.8 0.78 t (ms) 0.256 2.56 25.6 OUTPUT VOLTAGE 25.6 Table 14. 6-Bit PWM Ripple After Filtering Assuming RC filter (R=1kW) and V = 5V DD PWM Duty Cycle 50% Step = 5V/64 = 78mV which requires a minimum T (filter time constant) of 250ns x 64 x 64 / 4 = 256 S to ensure integral linearity of + / - 0.5 LSB. Figure 29. PWM Simplified Voltage Output After Filtering V DD PWMOUT 0V V DD OUTPUT VOLTAGE Vripple (mV) V OUTAVG 0V "CHARGE" "DISCHARGE" "CHARGE" "DISCHARGE" V DD PWMOUT 0V V DD V ripple (mV) OUTPUT VOLTAGE 0V "CHARGE" "DISCHARGE" "CHARGE" "DISCHARGE" VR01956 V OUTAVG 56/119 56 ST7272 DIGITAL TO ANALOG CONVERTER ( ont'd) C BRM Generation The BRM bits allow the addition of a 250ns-pulse to widen a standard PWM pulse for specific PWM cycles. This has the effect of "fine-tuning" the PWM Duty cycle (without modifying the base duty cycle), thus, with the external filtering, providing additional fine voltage steps. The incremental pulses (with duration of CLK = t 1/fCLK = 250ns) are added to the beginning of the original PWM pulse. The PWM intervals which are added to are specified in the 4-bit BRM register and are encoded as shown in the following table. The BRM values shown may be combined together to provide a summation of the incremental pulse intervals specified. The pulse increment corresponds to the PWM resolution. For example, if data 18h is written to the PWM register and data 06h (00000110b) to the BRM register, for a 4 MHz internal clock (250ns resolution), a 6.0 ms-long pulse will be output at 64ms intervals, except for cycles numbered #2,4,6,10,12,14, where the pulse is broadened to 6.25ms. Figure 30. BRM pulse addition (PWM > 0) m=0 16 s m=1 16 s Note. If 00h is written to both PWM and BRM registers, the generator output will remain at "0". Conversely, if both registers hold data 3Fh and 0Fh, respectively, the output will remain at "1" for all intervals #1 i #15, but it will return to zero at interval #0 for an amount of time corresponding to the PWM resolution (250ns). An output can be set to a continuous "1" level by clearing the PWM and BRM values and setting POL = "1" (inverted polarity) in the PWM register. This allows a PWM/BRM channel to be used as an additional I/O pin if the DAC function is not required. Table 15. Bit BRM Added Pulse Intervals (interval #0 not selected). BRM 4 - Bit Data 0000 0001 0010 0100 1000 Incremental Pulse Intervals none i=8 i = 4,12 i = 2,6,10,14 i = 1,3,5,7,9,11,13,15 m=2 16 s m = 15 16 s 6s 250ns increment VR01953 57/119 57 ST7272 DIGITAL TO ANALOG CONVERTER ( ont'd) C Figure 31. Simplified Filtered Voltage Output Schematic with BRM added = V DD PWMOUT 0V V DD OUTPUT VOLTAGE V OUTAVG BRM=1 BRM=0 = = 0V 250ns BRM EXTENDED PULSE VR01958 Figure 32. Graphical Representation of 4-Bit BRM added pulse Positions 58/119 58 ST7272 DIGITAL TO ANALOG CONVERTER ( ont'd) C 4.5.2.2 12-Bit PWM/BRM The 12 Bits of the two channels of the 12-bit PWM/BRM generator are distributed as 6 PWM bits and 6 BRM bits. The two 12-bit channels correspond to PWM0 and PWM1, and outputs DA0 and DA1 respectively. PWM Generation The functionality of the PWM generation is equivalent to the PWM generation of the 10-bit PWM/BRM described in the previous paragraph and so will not be repeated here. Please refer to the previous paragraph for functionality, to be used in conjunction with the following Register description. BRM Generation A 6-bit BRM register defining the intervals where an incremental pulse (with duration of CLK = t 1/fCLK=250ns) is added to the beginning of the original PWM pulse. BRM 6 - Bit Data 000000 000001 000010 000100 001000 010000 100000 Incremental Pulse Intervals none i = 32 i = 16,48 i = 8,24,40,56 i = 4,12,20,28,36,44.52,60 i = 2,6,10,...50,54,58,62 i = 1,3,5,7,9,...55,59,61,63 4.5.3 Register Description 4.5.3.1 10-bit PWM/BRM REGISTERS On a channel basis, the 10 bits are separated into two data registers: A 6-bit PWM register corresponding to the binary weight of the PWM pulse. A 4-bit BRM register defining the intervals where an incremental pulse is added to the beginning of the original PWM pulse. Two BRM channel values share the same register. (PWM 2:17) PULSE BINARY WEIGHT REGISTER (see register map) Read / Write Reset Value 1000 0000 (80 h) 7 1 POL P5 P4 P3 P2 P1 0 P0 b7 = Reserved (read as a "1") b6 = POL Polarity Bit. When POL is set, output signal polarity is inverse; otherwise, no change occurs. b5-0 = P5-P0 PWM Pulse Binary Weight for channel i Figure 33. Precision for PWM/BRM Tuning for VOUTEFF (After filtering) 59/119 59 ST7272 DIGITAL TO ANALOG CONVERTER ( ont'd) C (BRM 2:17) BRM REGISTER (see register map) Read / Write Reset Value: 0000 0000 (00 h) 7 B7 B6 B5 B4 B3 B2 B1 0 B0 (BWM 0:1) BRM REGISTER Register BRMi, i=0,1 Reset Value: 1100 0000 (00 h) 7 1 1 B5 B4 B3 B2 B1 0 B0 b7-4 = B7-B4 BRM Bits (channel i+1) b3-0 = B3-B0 BRM Bits (channel i) 12-bit PWM/BRM REGISTERS For each of the two channels, the 12 bits are separated into two data registers: A 6-bit PWM register corresponding to the binary weight of the PWM pulse. A 6-bit BRM register defining the intervals where incremental pulses are added to the beginning of the original PWM pulse. (PWM 0:1) PULSE BINARY WEIGHT REGISTER (see register map) Read / Write Reset Value: 1000 0000 (80 h) b7-6 = Unused b5-0 = B5-B0 BRM Bits (channel i) Note: From the programmer's point of view, the PWM and BRM registers can be regarded as being combined to give one data value. PWM/BRM OUTPUTS The PWM/BRM outputs are assigned to the following pins (unless otherwise stated, they are 10-Bit PWM/BRM, push-pull/open-drain output (0-V ) DD configuration): PWM/BRM 7 1 POL P5 P4 P3 P2 P1 0 P0 Pin DA.0 DA.1 DA.2 DA.3 DA.4 DA.5 DA.6 DA.7 DA.8 PWM/BRM 9 10 11 12 13 14 15 16 17 Pin DA.9 DA.10 DA.11 DA.12 DA.13 DA.14 DA.15 DA.16 DA.17 0 (1.2) 0 (1) 2 (2) 3 4 5 6 7 8 b7 = Reserved (read as a "1") b6 = POL Polarity Bit. When POL is set, output signal polarity is inverse; otherwise, no change occurs. b5-0 = P5-P0 PWM Pulse Binary Weight for channel i For example 0 Pol P P P P P P + B B B B Effective (with external RC filtering) DAC value 0 Pol P P P P P P B B B B 60/119 60 ST7272 4.6 EAST-WEST PIN CUSHION CORRECTION 4.6.1 Introduction The function of the East-West Pin Cushion Correction circuit (EWPCC) is to correct the horizontal synchronization timing signals to compensate for pin-cushion distortion on the display screen, normally caused by the magnetic display components.The EWPCC operates by storing, during monitor manufacrture, 256 coefficients related to the pin-cushion effect in a dedicated memory (EEPROM) and then implementing real-time correction by sending the stored coefficients out through the dedicated D/A Converter (DAC). The analog output is added (off-chip) to the deflection voltage that determines the starting point for the next line on the screen. These coefficients are uniformly distributed over the effective vertical refresh field of the screen. Figure 34. EWPC Coefficient Working on Pin-Cushion VOLTAGE "ADDED" TO DEFLECTION EWPCC OFFSETS (USER GENERATED TO MATCH PIN CUSHION EFFECT AND TO CANCEL IT) VERTICAL DISPLAY PERIOD 256 NEW SCREEN OUTLINE VR01946 61/119 61 ST7272 EWPCC (Cont'd) 4.6.2 Functional Description The EWPCC output is based on the signal present on the VFBACK input pin. The input signal is required to be asserted during the Vertical Fly-Back period (with a fixed positive polarity assumed). Warning: when the EWPCC is used, this I/O pin must be set to input mode; if the EWPCC is not used, the pin is available for normal I/O functions. For correct operation the MCU internal clock frequency must be 1024 times greater than the flyback frequency. Figure 35. EWPC Effective Action 0 1 2 3 MONITOR SCREEN 252 253 254 255 VFlyback 8 BIT DAC HORIZONTAL AMPLITUDE DYNAMIC MODULATION VR01945A 62/119 62 ST7272 EWPCC (Cont'd) In normal operation (after initialization), the EWPCC EEPROM is sequentially scanned by the address generator during the time interval that VFBACK is negated, that is during the active vertical display period. When VFBACK is asserted (flyback period) the address generator is reset, so that the address points to the first EEPROM posiFigure 36. VFBACK Input Timing tion and the DAC register is loaded with the first coefficient. The address generator consists of a 17-bit processor (8-bit up-counter + 9-bit up/down-counter), data/control registers and logic to minimize roundingup effect. Ver. total time: min. 5ms, max. 25ms (200Hz) (40Hz) VR01961C Sync. pulse width: typ. 400 s Figure 37. EWPCC Block Diagram CONTROL LOGIC f INT AND ADDRESS GENERATOR VFBACK SEL 1,0 SEL 1,0 MUX EEPROM MUX INTERNAL ADDRESS BUS ADDRESS TO EWPCC EEPROM INTERNAL DATA BUS VR01944 DAC EWPCC 63/119 63 ST7272 EWPCC (Cont'd) When the EWPCC function is disabled (SEL1,0 = [0,0]), the CPU may fill the EEPROM memory with the EWPCC coefficients calculated or measured during production test or transferred from a preset table within memory. In normal operation, when enabled, 256 analog levels on the EWPCC output (DAC analog output) are generated in evenly-spaced time/space intervals during the time that VFBACK is negated. To do so, the EWPCC performs two operating modes that are automatically chained once the sequence is triggered by writing a "1" to the INI control bit in the EWPCC1 register: a) Acquisition Mode: The output of the 8-bit prescaler, fed by the CPU clock (fCPU), is counted up by a 9-bit counter during the time that VFback is negated. The rising edge of VFback captures the 9-bit counter value and the 8-bit prescaler MSB into the data registers, as follows: Figure 38. Acquisition Mode Block Diagram 8-Bit Prescaler MSB ->> EWPCC0.0 9-Bit Counter 7 LSB's ->> EWPCC0.7,1 9-Bit Counter 2 MSB's ->> EWPCC1.1,0 Thus the 9-bit counter contains a value proportional to the duration of the "VFback low" condition. Since the lower 7 bits of the prescaler are not passed through to the next stage, there is an effective division by 256, thus the value in the counter may be considered as the number of INT cyf cles required to give the time of the complete nonretrace period equally divided by 256. The counter and the INI control bit (EWPCC1,2) are then automatically reset and the hardware is switched to the address generation mode. In order to minimize the truncation effect on the captured value accuracy, the overall 17-bit counter (8-bit prescaler + 9-bit counter) is preset to 00040h during assertion of VFBACK. f INT 8-Bit Up-Counter RST CLK MSB 9-Bit Up-Counter RST VFback D 9 INI RST Bit 0 D CLK REGISTER Bit 1-9 VR01950 64/119 64 ST7272 EWPCC (Cont'd) Figure 39. Acquisition Mode Timing CPU CLK Fback Counter Value 00040h 010AAh Capt EWPCC Data Reg. Reset Value 010AAh VR01948 Figure 40. Address Generation Mode Block Diagram f INT 9-Bit Down-Counter Zero CLK D MUX Toggle f INT 9 VFback Bit 9:1 Bit 0 REGISTER RST CLK 8-Bit Counter VR01947 65/119 65 ST7272 EWPCC (Cont'd) Figure 41. Address Clock Generation Mode (Division by N) CPU CLK Counter Value "1" Detection Load Modulus EEPROM Address Load DAC DAC REGISTER 03 02 01 N N -1 N -2 N-3 Address i Address i+1 Data m Data m+1 VR01952 Figure 42. Address Clock Generation Mode (Division by N + 1) CPU CLK Counter Value "0" Detection Load Modulus EEPROM Address Load DAC DAC REGISTER 03 02 01 00 N N-1 N-2 N-3 Address i Address i+1 Data m Data m+1 VR01949 66/119 66 ST7272 EWPCC (Cont'd) b) Address Generation Mode: Once the acquisition phase is complete, addresses are continuously issued to the EEPROM. The 17-bit processor is reconfigured as: - A 9-bit modulus (divide-by-N/N+1) down-counter, clocked by the CPU clock (fINT), and reloaded on zero detection with the value captured in the acquisition mode. - An 8-bit up-counter, clocked by zero detection in the 9-bit counter, which generates the EEPROM addresses. The division ratio N corresponds to the 9 MSB's of the value captured in the acquisition mode (EWPCC1,0 + EWPCC07,1) which is equivalent to the original number of f INT cycles to achieve the display time of VFBACK low divided by 256. The effect of this is then to divide the VFBACK time evenly by 256 and to increment the address to the EEPROM at each interval. The choice of N or N+1 is controlled by EWPCC0.0. If this bit is "0", the counter modulus is always N, otherwise an extra step is introduced into the counter to give N+1 and the counter divides by N and N+1 alternately. This algorithm performs a division by (N + 0.5). Note. After reset, the EWPCC function is disabled and the INI bit is cleared. By writing SEL1,0 = [1,1] and INI=1, the EWPCC function is enabled and the acquisition mode starts. 4.6.2.1 EWPCC Operation Modes The EEPROM content addressed by the address counter is loaded into the Digital to Analog converter (DAC) 8-bit data register through a multiplexer and then sent to the D/A Converter. The other input to the multiplexer is the internal Data Bus. This architecture allows the user the alternative of different configurations, selected by the control bits SEL1, 0. - SEL1, 0 = [1,1]: EWPCC Function Enabled (Normal Operation): EEPROM is addressed by the EWPCC Address Sequencer and its values directly sent to the DAC register through a dedicated bus. - SEL1,0 = [0,1]: EWPCC Function Disabled and Direct Loading (by a Single Instruction) to the DAC Register from the EEPROM through the dedicated bus. This direct transfer is synchronized with a dummy read instruction of the EEPROM with the addresses generated by the CPU. In this dummy operation, EEPROM data is not loaded onto the main data bus, but can be accessed by reading the DAC register. - SEL1,0 = [0,0] EWPCC Function Disabled. EEPROM and DAC in Stand-Alone Mode. Whenever the dedicated path between the EEPROM and the Digital to Analog Converter is enabled, after accessing the EEPROM, the byte read is sent to the DAC data register. If the DAC is configured as stand-alone, its data register is directly loaded by the CPU through the internal data bus. The architecture of the EWPCC circuit also gives the user the possibility (if necessary) of adjusting by software the captured value on the generation mode by writing into the EWPCC registers the new modulus that will be transferred to the counter upon the following underflow condition. The EWPCC function may also be used for the generation of other waveforms by suitable programming of the EWPCC EEPROM. Tolerance The truncation error on the acquired value corresponds to -0.25 < Error < 0.25 (with the algorithm used) which can be related to a maximum shift of 32ms on the vertical axis of the screen, at the 256th address (or a maximum 16ms at the 128th) with respect to the ideal case of zero truncation error when generating evenly-spaced intervals by dividing the time interval in which VFBACK is negated by 256. 67/119 67 ST7272 EWPCC (Cont'd) 4.6.3 Register Description (PCC0) EAST-WEST (000C h) CONTROL REGISTER b2 = INI: Acquisition Mode Initialization/Status Bit. Writing a "1" to INI triggers the acquisition mode, after detection of VFback rising edge. During this mode, INI is read as a "1". Once acquisition is completed, this bit is cleared by hardware and address generation mode is chained. b1-0 = M1-M0: 9-bit Counter Value MSB's. These bits correspond to the two most-significant bits of the captured value from the 9-bit counter on acquisition mode. Notes. When EWPCC mode is selected (SEL1,0 = [1,1]), any writing operation into the EEPROM control register is blocked by hardware. - When SEL0 = "1", the EEPROM value is not transferred onto the databus. - During acquisition mode, re-writing the INI control/status bit as "1" will not have any effect - the acquisition procedure already in progress will not be reset. Read/Write Reset Value: 0000 0000 (00h) 7 M7 M6 M5 M4 M3 M2 M1 0 M0 b7-1 = M7-M1: 9-Bit Counter 7 LSBs. These bits correspond to the 7 least-significant bits of the captured value from the 9-bit counter when in acquisition mode. b0 = M0: 8-Bit Prescaler MSB. This bit corresponds to the most significant bit of the 8-bit prescaler, captured during acquisition mode. (PCC1) EAST-WEST (000D h) CONTROL REGISTER Read / Write Reset Value: 1100 0000 (C0 h) 7 1 1 0 SEL1 SEL0 INI M1 0 M0 (DACR) EWPCC DAC REGISTER (000B h) Read/Write Reset Value: 0000 0000 (00h) 7 0 D6 D5 D4 D3 D2 D1 D0 b7-6 = Reserved (read as "1") b5 = Reserved MUST BE PROGRAMMED AS "0" b4-3 = SEL1,SEL0: Mode Selection Bits. These read/write bits allow selection of configuration, as follows: SEL1 SEL0 0 0 EWPCC Function Disabled EEPROM and DAC Stand Alone EWPCC Function Disabled EEPROM addressed by CPU and its data sent directly to Reserved EWPCC Function Enabled EEPROM addressed by EWPCC block Data sent to DAC Register D7 b7-0 = D7-D0: DAC Input Binary Byte. This byte corresponds to the binary value to be converted onto an analog signal. (CR3) EWPCC EEPROM CONTROL REGISTER (0011 h) This register contains the bits required to read, erase and program the EWPCC EEPROM. Please refer to the EEPROM chapter for details on using this register and for programming the EWPCC EEPROM. 0 1 1 1 0 1 68/119 68 ST7272 4.7 A/D CONVERTER (ADC) 4.7.1 Introduction The Analog to Digital converter is a single 8-bit successive approximation converter. Analog voltages from external sources are input to the converter through up to 6 pins (PB0 to PB7). The result of the conversion is stored in the 8-bit Result Data Register. The A/D converter is controlled through the A/D Converter Control/Status Register. 4.7.2 Functional Description The A/D converter is enabled by setting the A/D Converter ON bit (ADON) of the A/D Converter Control/Status Register. A delay time is then required for the converter to stabilize (see characterization section). When the A/D function is active, pins PB0 to PB7 can be used as analog inputs. The inputs must first be enabled for analog input by setting the corresponding bit(s) of the Port B Configuration Register as described in the Section on I/O Ports. Bits CH2 to CH0 of the A/D Converter Control/Status Register then select the channel to be converted. The high and low level reference voltages are connected to pins VDD and VSS. When enabled, the A/D converter performs a continuous conversion of the selected channel. When a conversion is completed (16 s for CPU = 4 f MHz), the result is loaded into the read only Result Data Register and the COCO (Conversion Complete) flag is set. No interrupt is generated. Any write to the A/D Converter Control/Status Register aborts the current conversion, resets the COCO flag and starts a new conversion. The A/D converter is ratiometric. An input voltage equal to, or greater than V , converts to FFh (full DD scale) without overflow indication if greater. An input voltage equal to, or lower than V converts to SS 00h. The conversion is monotonic: the results never decrease if the analog input does not and never increase if the analog input does not. Each step of conversion is equal to VDD divided by 256: thus the conversion result is expressed as 8 bits, with a maximum error corresponding to three conversion steps. Using a pin, or pins, as analog inputs does not affect the ability to read port B as logic inputs. The minimal conversion time is 32 ADC clock cycles (16us if A/D clock frequency at 2 MHz). The A/D converter clock is generated from the CPU clock divided by 2. The A/D converter can be disabled by resetting the ADON bit. This feature allows the reduction of power consumption when no conversion is in progress. The A/D converter is disabled after Power-On and external resets. The A/D converter is not affected by WAIT mode but, in power sensitive applications, it can be switched off before entering this mode. When the MCU enters the HALT mode with the A/D converter enabled, the A/D clocks are stopped and the converter is disabled until the HALT mode is exited and the start-up delay has elapsed. A stabilisation time is also required before accurate conversions can be performed. The converter uses the power supply lines as voltage refernces, consequently conversion accuracy may be degraded by voltage drops in the event of heavily loaded power supply lines. 69/119 69 ST7272 A/D CONVERTER (Cont'd) 4.7.3 Register Description A/D CONTROL/STATUS REGISTER (CSR) Address: 0071h -- Read/Write Reset condition: 00 h 7 COCO 0 ADON 0 CH2 CH1 0 CH0 Bit-3: Reserved, must be programmed to 0 Bits 2-0: CH2-CH0 Channel Selection These bits select the analog input to convert. CH2-CH0 000 001 010 011 100 101 Pin PC0 PC1 PC2 PC3 PC4 PC5 Channel AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 Bit-7: COCO Conversion Complete. COCO is set as soon as a new conversion can be read from the Result Data Register. COCO is cleared by reading the result or writing to the A/D Converter Control/Status Register. Bit-6: Reserved, must be programmed to 0 Bit-5: ADON A/D converter On. ADON allows the A/D converter to be switched on and off in order to reduce consumption when needed. When turned on (ADON = 1), a delay time (typically 10us) is necessary for the current to stabilize. Conversions can be inaccurate during this time. Bit-4: Not used A/D DATA REGISTER (DR) Address: 0070h 7 AD7 AD6 AD5 AD4 AD3 AD2 AD1 -- Read Only 0 AD0 Reset condition: (undefined) Bits 7-0: AD7-AD0 Analog Converted Value. 70/119 70 ST7272 4.8 DDC BUS INTERFACE (DDC) 4.8.1 Introduction The DDC Bus Interface is an extension of the 2C I Bus Interface. In addition to the Multiple Master/Slave I2C DDC2A modes, both DDC1 and DDC2B modes can be handled. Thanks to the presence of a Direct Memory Access channel, the interface can transfer data bytes with the minimum CPU overhead at all DDC levels. 4.8.1.1 DDC Features: - I2C, DDC1 and DDC2B modes. - Programmable automatic switchover from DDC1 to I2C mode. - DMA transfer/1 byte transfer. - Interrupt generation for error conditions. - Interrupt generation for transfer request. 4.8.1.2 I2C Features: - Parallel-bus to I2C protocol conversion. Figure 43. I2C Block Diagram DATA BUS - Multi-master capability. - 7-bit Addressing. - Transmitter/Receiver flag. - End of Byte transmission flag. 4.8.1.3 I2C Master Features: - Clock generation 2 - Flag indicating when the I C bus is in use - Flag indicating the loss of arbitration 4.8.1.4 I2C Slave Features: - Start bit detection flag - Detection of a misplaced Start or Stop condition - Detection of a problem during the transfer - I2C Address Matched detection - DDC2B Address Matched Detection DATA REGISTER DATA SHIFT REGISTER SDA DATA CONTROL COMPARATOR OWN ADDRE SS REGISTER DDC2B ADDRESS CLOCK CONTROL REGISTER SCL Vsync CLOCK CONTROL STATU S REGISTER 1 STATU S REGISTER 2 CONTROL REGISTER DMA IT BUFF LOGIC DMAACK CONTROL SIGNAL S INTER RUPT 71/119 71 ST7272 DDC BUS INTERFACE (Cont'd) 4.8.2 Functional Description The DDC Interface serves as an I/O interface between the MCU and the Display Data Channel protocol. In addition to receiving and transmitting data, the interface converts data from serial to parallel format and vice versa, using an interrupt or polled handshake. The interface is able to operate 2 in two different modes: DDC1 and I C, with a special DDC2B dedicated function. It can transfer a data byte in as little as two CPU clock cycles, using Direct Memory Access (DMA). The DDC Interface is externally connected by a data line (SDA) and by two clock lines (SCL and VSYNC); the SDA and the SCL lines are connected Figure 44. DDC/DMA Cell Block Diagram . to an I2C bus. The interface is connected to the CPU by an interrupt (IT ERR), and to the DMAREQ input of the DMA by an output signal (IT BUFF), as well as to the DMAACK output of the DMA by an input (DMAACK). In the DDC protocol, there are two types of communication protocols which are called DDC1 and DDC2. In DDC2B communication protocol, the interface operates in Multimaster/Slave I2C mode. So, the selection of these protocols can be made by software, by using the I2C mode (see I2C mode) DDC Memory CPU Address bus Data bus RW IT BUFF DMA REQ DMA ACK SUSP HOLD DMA DDC and DMA interrupts 72/119 72 RW DDC Interrupt ST7272 DDC BUS INTERFACE (Cont'd) The DDC Interface makes use of seven internal register locations. Three of these are used for interface initialization (Own Address Registers and Clock Control Register), while the remaining four are used during data transmission/reception (Data Register, Control Register and Status Registers). The SCL frequency (FSCL) is controlled by a programmable clock divider which depends on the I2C bus mode. The interface address is stored by software in the OAR1 register . For DDC1 operation, DMA must be used to handle data transfer automatically, without placing an extra burden on the CPU. Following a Reset, the interface is disabled. DDC1 mode is selected by software. In DDC1 mode, I2C mode selection is made by software or by the detecting a "high" to "low" transition on the SCL line. 4.8.2.1 DDC1 mode In DDC1 mode, the interface reads data bytes from memory using DMA, which it then transmits as 8-bit bytes, MSB first. Data bits are clocked on the rising edge of VSYNC, which is received by the interface at a maximum frequency of 25 KHz. A ninth clock pulse, during which the interface expects to receive an acknowledge, follows the eight Table 16. DDC Levels. DDC Level 1 Cell Mode Comments Possible Automatic DDC1 H/W mode w/o Int DDC1 Possible Automatic DDC1->2B H/W switch VSyncI1 is used as clock. (up to 25 kHz) Enable DDC2B A0/A1 I2C decoding address 2B clock cycles of the byte transfer. Prior to each transfer, the interface sets the IT BUFF interrupt to signal a DMA transfer request, then waits for the DMA to issue the DMAACK signal. Data transfer between the DDC cell and memory will then begin on the subsequent rising edge of V SYNC. 4.8.2.2 DDC2B mode In DDC2 mode, the interface actually operates in 2 I2C Mode, but the extra A0/A1 I C address is enabled in addition to the standard programmable address (6E). To enable the DDC2B A0/A1 2C adI dress comparator, DDC2BEN must be set. In DDC2A mode, the A0/A1 address should be disabled by clearing the same bit. 4.8.2.3 I2C Mode In I2C mode, the interface can operate in the following four modes: - Master Transmitter - Master Receiver - Slave Transmitter - Slave Receiver When it is inactive, it operates in Slave mode. I2C Slave I2C Multi-Master/Slave Set the I2C address at 6E DMA allows automatic EDID & extEDID transfer CPU Load minimized with DMA data block transfer DDC/DMA cell maximizes speed transmission and take minimum Access Bus bandwidth 2AB DDC Level 1 2B 2AB (A.Bus) DDC1 Yes No No DDC2B Yes Yes No I2C Master Transmitter No No Yes I2C Master Receiver No No No** I2C Slave Transmitter No* Yes No** I2C Slave Receiver No* Yes Yes (*): Programmable automatic H/W DDC1 -> DDC2B transition (**): Slave Transmitter and Master Receiver modes are not used by Access Bus I 2 C protocol. 73/119 73 ST7272 DDC BUS INTERFACE (Cont'd) The DDC interface allows Multimaster operation, thanks to automatic switching between Master and Slave mode in the event of a loss of arbitration. The slave process is therefore always active when a Start condition is detected on the SDA line. When acting as Master, a data transfer is initiated and the clock signal is generated. A serial data transfer always begins with a Start condition and ends with a Stop condition. Both Start and Stop conditions are generated by software in Master mode. In Slave mode, the Own Address, or the DDC2B address are recognised. DDC2B mode is enabled and disabled by software. Data and addresses are transferred as 8-bit bytes, MSB first. The first byte following the Start condition is the address byte; it is always transmitted in Master mode. A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Acknowledge is enabled and disabled by software. In Slave transmitter mode, the interface is able to convert data formats between the micro-controller and the I2C bus directly or by using DMA. In the first case, it waits for the MCU to write in the Data Register before transmission of a data byte, or to read the Data Register following reception of of a data byte, by holding the SCL line low. In the latter case, the interface sets the IT BUFF interrupt to signal a request for DMA transfer, then waits for the DMA to set the DMAACK signal. Transfer be2 tween the interface and the I C bus will begin on the next rising edge of VSYNC. For further information relating to practical implementation, consult the relevant Application Notes for I2C, Access Bus, DDC1/2B and DDC1/2AB management. 7 0 D6 D5 D4 D3 D2 D1 0 D0 bit 7: Must be set to "0" for correct operation. D6-D0: 7-bit divider programming In I2C mode: FSCL = PHI1/(2x([D6..D0]+2)) DDC DATA REGISTER (DR) Address: 0056h -- Read / Write Reset condition: 0000 0000 (00 h) 7 DR7 DR6 DR5 DR4 DR3 DR2 DR1 0 DR0 In transmit mode, DR contains the next byte of data which is to be loaded into the shift register. Transmission of the byte begins after the MCU has written to DR, or on the subsequent rising edge of VSYNC, if DMAACK is set. In receive mode, DR contains the last byte of data received from the shift register. Reception of the next byte begins after the MCU has read DR, or on the subsequent rising edge of V SYNC if DMAACK is set. DDC OWN ADDRESS REGISTER1 (OAR1) Address: 0054h -- Read/Write Reset condition: 0000 0000 (00 h) 7 0 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 4.8.3 Register Descriptions DDC CLOCK CONTROL REGISTER (CCR) Address: 0053h -- Read/Write ADD7 ADD7-ADD1 represent the peripheral address in I2C mode ADD0 is the Data Direction bit. Reset condition: 0000 0000 (00 h) 74/119 74 ST7272 DDC BUS INTERFACE (Cont'd) DDC CONTROL REGISTER (CR) Address: 0050h -- Read/Write Reset condition: 0000 0000 (00 h) 7 DDC1 TRANS PE DDC 2BEN Start Ack Stop 0 ITE Reset. This bit is not cleared by hardware in slave mode. ACK: Acknowledge level When this bit is set, an acknowledge is returned after an address byte is received or after a data byte is received.When it is cleared, no acknowledge is returned.It is set by software and it is cleared by software, when the peripheral is disabled (PE=0) or by reset. 2 START: Generation of Start condition (I C mode) ITE: Interrupt Enable When the Interrupt Enable bit is set, the DDC interface interrupts (IT ERR and IT BUFF) are generated after anyone of these following conditions: 2 - A Start condition is generated in I C Master Mode (IT ERR). - The address is matched in I2C slave mode while the ACK flag is at a logic high (IT ERR). - A data byte has been received or is to be transmitted (IT BUFF). - A loss of arbitration of the bus to another master in I2C master mode (IT ERR). - A misplaced Start or Stop condition is detected (IT ERR). 2 - There is no acknowledge in I C transmitter mode (IT ERR). 2 - A Stop condition has been detected in I C slave mode (IT ERR). When the Start bit is set in slave mode, the interface generates a Start condition as soon as the bus is free. In master mode, it generates a repeated Start condition. Then an interrupt is generated if ITE is set.This bit is set by software and is cleared by software, when the peripheral is disabled (PE=0) or by reset. It is automatically cleared after the start condition is sent. DDC2EN: Enable DDC2B model When this bit is set, the peripheral acknowledges the A0/A1 call address.DDC2BEN bit is set or cleared by software. It is cleared when the peripheral is disabled (PE=0) or by reset. PE: Peripheral Enable 1: Master/Slave capability. 0: Peripheral disabled (all outputs will be released after the end of the current byte transmission). When this bit is reset, all the bits of the control register and the status register except the Stop bit are reset. PE selects the alternate function on the corresponding I/O. This bit is set by software and cleared by software. TRANS: Automatic transition mode(DDC1EN set) 1: A falling edge on SCL line will automatically switch from DDC1 to I2C modes (SCLFAL is set). 0: No automatic transition. DDC1EN: DDC1/I2C mode selection When the DDC1EN bit is set then the interface op2 erates in DDC1 mode else it operates in I C mode.The DDC1EN bit is set by software. It is cleared by software, when both the SCLFAL flag and the TRANS flag are set, when the peripheral is disabled (PE=0) or by a reset. 75/119 - A high to low transition on SCL line has been detected in DDC1 mode if the TRANS flag is set (IT ERR). If the ITE flag is set, an interrupt is generated, SCL is hold low and the transfer is suspended except when a loss of arbitration or a detection of a Stop condition have been detected. ITE is reset by software, when the peripheral is disabled (PE=0) or by reset. 2 STOP: Generation of Stop condition (I C mode) If the Stop bit is set in master mode, then a Stop condition is generated after the transfer of the current byte, or after the current Start condition is sent. If it is set in slave mode, then both SCL and SDA lines are released at the end of the current byte in order to recover from an error condition, and the peripheral waits for the detection of a Start or Stop condition. This bit can be cleared by software. It is automatically cleared after the Stop condition is sent on the SCL line in master mode or by 75 ST7272 DDC BUS INTERFACE (Cont'd) DDC FIRST STATUS REGISTER (SR1) Address: 0051 h -- Read Only It is also cleared when the peripheral is disabled (PE=0) or on Reset. When BTF is set, the DDC interrupt (IT BUFF) occurs if ITE is set. The MCU must then access the Data Register, or the DMA must set the DMAACK signal. BUSY: Bus Busy (I2C mode) The BUSY bit is active when there is a communication in progress. Detection of communications is always active (even if the peripheral is disabled). This bit is set on detection of a Start condition, and it is cleared on detection of a Stop condition. It is also cleared when the peripheral is disabled (PE=0) or on Reset. TRA: Transmission mode The TRA bit is set when the interface is in data transmission mode. TRA is cleared on detection of a Stop condition or in the event of a loss of bus arbitration (ARLO set). It is also cleared when the peripheral is disabled (PE=0) or on Reset. In DDC1 mode, TRA is always set. ITFLAG: Interrupt Flag The ITFLAG bit is set after any of the following conditions: 2 - A Start condition is generated in I C Master Mode. 2 - The address is matched (in I C Slave mode) while the ACK flag is set to "1". Reset condition: 0000 0000 (00 h) 7 ITFLAG 0 TRA BUSY BTF ADSL M/SL 0 SB SB: Start Bit (I2C master mode) In master mode, SB bit is set when the hardware has generated a Start condition. When this bit is set, an interrupt (IT ERR) is sent to the micro-controller if ITE is set. Then the micro-controller must write the address byte in the data register.This bit is cleared by a read of the status register (when SB is set), followed by a write in the data register. It is also cleared when the peripheral is disabled (PE=0) or by reset. M/SL: Master/Slave (I C mode) The M/SL bit is set when the interface generates a Start condition. When it is set, the interface operates in master mode.It is cleared by the generation of a Stop condition, by a loss of arbitration, by reset or when the peripheral is disabled (PE=0). ADSL: Addressed as Slave (I2C mode) ADSL bit is set when the address comparator recognizes either its own slave address or the DDC2B address. When this bit is set, an interrupt (IT ERR) is sent to the micro-controller if ITE is set. This bit is cleared by reading the status register (when ADSL is set). It is also cleared when the peripheral is disabled (PE=0) or by reset. BTF: Byte Transmission Finished In transmit mode, the BTF bit is set after the transmission of a data byte and an acknowledge clock pulse. It is cleared by reading the Status Register (with BTF set), followed by writing to the Data Register, or when DMAACK is set. In receive mode, the BTF bit is set following reception of a byte acknowledge. It is cleared by reading the Status Register (with BTF set), followed by reading the Data Register, or when DMAACK is set. While the DDC1 flag is set, BTF is the only source of the IT BUFF interrupt (if ITE is set). 76/119 2 - A data byte has been received or is to be transmitted. - In the event of the loss of bus arbitration to another master, while in I2C master mode. - On detection of a misplaced Start or Stop condition. 2 - When there is no acknowledge in I C transmitter mode. - A Stop condition has been detected in 2C slave I mode. - A high to low transition has been detected on the SCL line in DDC1 mode, while the TRANS flag is set. This bit is cleared when SR2 is read, when the peripheral is disabled (PE=0) or by reset. 76 ST7272 DDC BUS INTERFACE (Cont'd) DC SECOND STATUS REGISTER (SR2) Address: 0052h -- Read Only Reset condition: 0000 0000 (00 h) 7 SCLFAL 0 0 AF STOPF ARLO BERR 0 DDC2BF cleared by a reading of the Status Register or by a reset. SCLFAL: SCL Falling Edge (DDC1 mode) This bit is set on detecting an SCL falling edge while the DDC1EN flag is set. While the DDC1 flag is set, SCLFAL is the only source of the IT ERR interrupt, providing ITE is set. All other flags in SR2 are disabled. During this interrupt the SCL line is not held low. The SCLFAL bit is cleared by reading the Status Register. DDC2BF: If DDC2BEN is set, DDC2BF is set on detection of the DDC2B A0/A1 address. It is cleared on detection of a Stop condition, on Reset, or when the peripheral is disabled (PE=0). BERR: Bus Error (I2C mode) The BERR bit is set on detection of a misplaced Start or Stop condition. If this bit is set, an interrupt (IT ERR) is sent to the MCU, providing ITE is set. During this interrupt, the SCL line is not held low. The Bus Error flag bit is cleared by reading the Status Register (while BERR is set). A bus error is not internally considered as a Stop or a Start. The bit is also cleared when the peripheral is disabled (PE=0), or on Reset. ARLO: Arbitration Lost (I2C master mode) 2 The ARLO bit is set when the I C interface loses arbitration of the bus in favour of another Master. Once ARLO has been set, the interface will operate in Slave mode (M/SL at a logic low) and an interrupt (IT ERR) is generated, providing ITE is set. During this interrupt, the SCL line is not held low. The ARLO bit is cleared by reading the Status Register. It is also cleared when the peripheral is disabled (PE=0) or on Reset. STOPF: Stop Detection (I2C Slave mode) The STOPF bit is set when a Stop condition is detected on the SCL line after an acknowledge of byte.When this bit is set, an interrupt (IT ERR) is sent to the micro-controller if ITE is set. During this interrupt, the SCL line is not hold low.This bit is cleared by a read of the status register (when StopF is set). It is also cleared when the peripheral is disabled (PE=0) or by reset. AF: Acknowledge Failure (I2C mode) The Acknowledge Failure bit is set when there is a problem during the transfer. If this bit is set, then an interrupt (IT ERR) is sent to the micro-controller if ITE is set. During this interrupt, the SCL line is not hold low. The Acknowledge Failure bit is Table 17. DDC Register Map A2 1 1 1 0 0 0 0 A1 1 0 0 1 1 0 0 A0 0 1 0 1 0 1 0 Register DR Reserved OAR1 CCR SR2 SR1 CR 4.8.4 DDC1 Mode In order to enter DDC1 mode, the PE flag and the DDC1EN flag must be set. Bytes are sent on the rising edge of VSYNC on the SDA line, MSB first. A ninth clock pulse follows the 8 clock cycles of a byte transfer. During this ninth clock pulse an acknowledge bit is sent, providing the ACK bit is set. The DDC1EN bit is then cleared and an interrupt (IT ERR) is generated. This interrupt is cleared by reading the Status Register. 4.8.5 I2C Mode Following a Reset, the DDC interface operates in I2C mode. When the interface is operating in 2 DDC1 mode, it will automatically switch to I C mode on detecting a falling edge on the SCL line. In order to enter I2C mode, the PE bit must be set and the DDC1EN bit must be cleared. 4.8.6 I2C State Machine In I2C mode, the DDC interface always operates in Slave mode (M/SL "low"), except when it initiates a transmission or a receive sequence. Multimaster mode is implemented by automatically switching from Master mode to Slave mode when the interface loses arbitration of the 2C bus. I 77/119 77 ST7272 DDC BUS INTERFACE (Cont'd) 4.8.7 Slave Mode As soon as a Start condition is detected, the address word is received on the SDA line and transferred to the shift register; it is then compared with the interface address, whereupon one of the following two conditions are possible: - Address does not match: the state machine is reset and awaits another Start bit. - Address matches: the "Addressed As Slave" bit (ADSL) is set and an Acknowledge bit is sent to the Master, providing ACK is set. An interrupt is thus sent to the MCU if ITE is set. The interface then waits for the MCU to read Status Register 1, by holding the SCL line low. Next, depending on the state of the Data Direction bit (LSB), and after issuing an acknowledge, the Slave must enter transmit or in a receive mode. 4.8.7.1 Slave Sending The Slave device waits for the MCU to write to the Data Register, or waits for the DMA controller to set DMAACK by holding the SCL line low. Data is then moved into the Shift Register and transmitted on the SDA line. - When the acknowledge bit is received, the BTF flag is set and an interrupt (IT BUFF) is generated if ITE is set. - On detection of a Stop or Start condition during a byte transfer, the BERR flag is set, and an interrupt (IT ERR) is generated. - On detection of a Start condition after the expiry of an acknowledge time-slot, the state machine is reset and begins a new process. The ADSL flag is set and an interrupt (IT ERR) is generated if ITE is set. - On detection of a Stop condition after the expiry of an acknowledge time-slot, the state machine is reset. The STOPF flag is set and an interrupt (IT ERR) is generated if ITE is set. 4.8.7.2 Slave Receiving The Slave receives words on the SDA line which are transferred to the shift register, these are then forwarded to the Data Register. After each word, an acknowledge bit is issued, providing the Enable Acknowledge flag is set. When the acknowledge bit is sent, the BTF flag is set and an interrupt (IT BUFF) is generated if ITE is set.The interface then waits for the MCU to read the Data Register, or for the DMA to set DMAACK by holding the SCL line low. The following conditions are possible: - On detecting a Stop or Start condition during byte reception, the BERR flag is set and an interrupt (IT ERR) is generated. - On detecting a Start condition after expiry of an acknowledge time-slot, the state machine is reset and begins a new process. - On detecting a Stop condition after the expiry of an acknowledge time-slot, the Slave state machine is reset. The STOPF flag is then set and an interrupt (IT ERR) is generated if ITE is set. - The Stop bit in the Control register is set: the State machine is reset after transfering the current byte. 78/119 78 ST7272 DDC BUS INTERFACE (Cont'd) 4.8.8 Master Mode The interface operates in Master mode after generating a Start condition. Therefore the Start flag must be set in the Control register and the 2C bus I must be free (Busy bit "low"). Once the Start condition is generated, the M/SL and SB flags are set and an interrupt (IT ERR) is generated if ITE is set. The interface waits for the micro-controller to write the slave address to the Data Register, by holding the SCL line low. Then the address byte is sent on the SDA line, an acknowledge clock pulse is sent on the SCL line, and an interrupt (IT ERR) is generated if ITE is set. The interface waits for the MCU to write to the Control Register by holding the SCL line low. If there is no acknowledge, the AF flag is set and the master must write Start or Stop in the Control Register. The state machine then enters a send or receive process, depending on the status of the Data Direction bit (LSB); an interrupt (IT BUFF) is generated if ITE is set. If the master loses bus arbitration, or if there is no acknowledge, the AF flag is set and the master must write a Start or a Stop in the Control register. The ARLO flag is set, the M/SL flag is cleared and the process is reset. An interrupt (IT ERR) is generated if ITE is set. 4.8.8.1 Master Sending The Master waits for the MCU to write to the Data Register or for the DMA controller to set DMAACK by holding the SCL line low. The byte is loaded into the shift register and sent on the SDA line. The BTF flag is set and an interrupt (IT BUFF) is generated if ITE is set. - On detection of a Stop or a Start condition during a byte transfer, the BERR flag is set and an interrupt is generated if ITE is set. - If the Stop bit is set in the Control Register, a Stop condition is generated after the current byte has been transferred, the M/SL flag is cleared and the state machine is reset. Then an interrupt is generated if ITE is set. - If the Start bit is set in the Control Register, the state machine is reset and begins a new process. The SB flag is set and an interrupt (IT ERR) is generated if ITE is set. - If there is no acknowledge, the AF flag is set and an interrupt is generated if ITE is set. 4.8.8.2 Master Receiving The Master receives a byte from the SDA line into the shift register and then transfers it to the Data Register. An acknowledge bit is genertated if the ACK bit is set and an interrupt is generated (IT BUFF) if ITE is set. The interface then waits for the MCU to read the Data Register or for the DMA controller to set DMAACK by holding the SCL line low. On detection of a Stop or Start condition during reception of a byte, the BERR flag is set and an interrupt (IT ERR) is generated if ITE is set. If the Stop bit is set in the Control Register, a Stop condition is generated following transfer of the current byte; the M/SL flag is cleared and the state machine is reset. Then an interrupt (IT ERR) is generated if ITE is set. If the Start bit is set in the Control Register, the state machine is reset and begins a new process. The SB flag is set and an interrupt (IT ERR) is generated if ITE is set. 79/119 79 ST7272 DDC BUS INTERFACE (Cont'd) 4.8.9 Transfer sequencing Master Transmitter (I2C mode): S IT1 Add A IT2 IT3 Data A IT3 Data A IT3 P IT1: SB =1. Cleared by a read of SR1 followed by a write to the DR (IT ERR). IT2: Cleared by a read of SR1 followed by a write to the CR. IT3: BTF=1; TRA=1. Cleared by reading SR1 followed by writing to the DR, or cleared when DMAACK is set (IT BUFF). Master Receiver (I2C mode): S IT1 Add A IT4 Data A IT5 Data A IT5 P IT4: Cleared by reading SR1 followed by writing to the CR. IT5: BTF=1; TRA=1. Cleared by reading SR1 followed by reading the DR, or cleared when DMAACK is set. Slave Transmitter (I2C mode): S Add A IT6 IT7 Data A IT7 Data A IT7 P IT8 IT6: ADSL =1. Cleared by reading SR1. IT7: BTF=1. Cleared by reading SR1, followed by writing to the DR, or cleared when DMAACK is set. IT8: STOPF=1. Cleared by reading SR2. Slave Receiver (I2C mode): S Add A IT9 Data A IT10 Data A IT10 P IT8 IT9: ADSL =1. Cleared by reading SR1. IT10: BTF=1. Cleared by reading SR1 followed by reading the DR, or cleared when DMAACK is set. Slave Transmitter (DDC1 mode): IT12 Data A IT12 Data A IT12 IT12: BTF=1; TRA=1. Cleared by reading SR1 followed by writing to the DR, or cleared when DMAACK is set. S: Start; P: Stop; A: Acknowledge; IT: interrupt Detailed timing information is available inSection 6 ELECTRICAL CHARACTERISTICS. 80/119 80 ST7272 4.9 DDC DMA CHANNEL (DDC-DMA) 4.9.1 Introduction The DMA channel is associated with the DDC peripheral interface and handles direct accesses to RAM memory as required by the peripheral. When a DMA access is performed the CPU must not be in WAIT mode: before executing a WAIT instruction, the DMA must therefore be disabled, if necessary. 4.9.2 Main Features - Single DMA channel for management of direct memory access by the DDC peripheral. - 16-bit Initial Address Register (IADHR, IADLR) - 16-bit Current Address Register (CADHR, CADLR) - 8-bit Initial Counter Register (ICTR) - 8-bit Current Counter Register (CCTR) - 8-bit Control Register (CTLR) - Address incrementing and decrementing following each transfer. - Counter decrementing following each transfer. - Auto reload and linear modes. - Daisy-chained DMA capability. - DMA transfer performed in only 2 CPU cycles. 4.9.3 Functional Description The DDC-DMA channel allows direct transfer between the DDC peripheral and memory. The transfer can be from DDC cell to memory or vice versa, depending on the state of the RW bit in the DMA Control Register. The DMAREQ signal causes the DMA cell to stop the CPU clock for 2 cycles on the subsequent opcode fetch or immediately if the CPU is in WAIT state (by setting HOLD signal). During these two cycles, the CPU releases the address bus and the control signal lines used to synchronize bus accesses. During DMA operations, memory is accessed in exactly the same way as it normally is by the CPU. The contents of the CADHR and CADLR registers is output to the address bus, and the RW signal is driven in accordance with the RW bit setting. If DMA is disabled when a peripheral requests it, the DMA cell simply transmits the request to the CPU using an interrupt line. The DMA request will then be serviced as an interrupt request. 4.9.4 DMA Control Signals DMAREQ: DMA REQuest (input from the peripheral). The peripheral associated with the DMA channel generates this input signal in order to request a DMA transfer. The transfer will occur on the subsequent op-code fetch, or immediately, if the CPU is in WAIT mode. The DMA cell knows when the op-code fetch occurred, by monitoring the LI signal from the CPU. HOLD: HOLD CPU (output to the CPU). This output is generated during DMA transfer, in order to put the CPU in Hold. The CPU releases the RW signal line and the address bus. The CPU clock is stopped. DMAACK: DMA ACKnowledge (output to the peripheral). This output is generated during a DMA transfer, when the peripheral can read (RW bit = 1) or write (RW bit = 0) the data present on the data bus. RW: Read/Write (input/output) During a DMA transfer, the RW signal is defined as an output signal and its value correspond to RW-bit. In the others cases, RW is an input coming from the CPU (RW=1:read; RW=0 write) A0-15: Address bus (input/output) During a DMA transfer, Address bus bits A0-15 are defined as outputs and their value corresponds to the value of the CADR. In all other cases, A0-15 are inputs coming from the CPU. 81/119 81 ST7272 DDC-DMA (Cont'd) 4.9.5 DDC DMA Channel (DDC-DMA) Register Descriptions DMA INITIAL ADDRESS REGISTER (IADHR & IADLR) Addresses:0048 & 0049h -- Read / Write affected by RESET or when the DMA is disabled.The CCTR is a read/write register. DMA CONTROL REGISTER (CTLR) Address: 004E h -- Read / Write Reset condition: XXXX XXXX (XX h) Reset condition: 0000 0000 (00 h) 7 MATCH 0 EN ITE RW DECR AUTOR 0 SUSP This 16-bit register pair contains the initial address for the DMA transfer. It is not affected by Reset or by disabling the DMA. Read accesses are always allowed. Write accesses are allowed only in Suspend Mode (SUSP bit "high"). MATCH: Match to 00h - Set by hardware when CCTR reaches 00h (end of a block transmission). If the ITE bit is set, an interrupt request is sent to the CPU. - Reset by Reset or by software. DMA CURRENT ADDRESS REGISTER(CADHR & CADLR) Addresses: 004A & 004B h -- Read / Write Reset condition: XXXX XXXX (XX h) This 16-bit register pair contains the address of the next DMA transfer. It is not affected by Reset or by disabling the DMA. Note: As MATCH is set by the DMA when the CPU is activity is stopped, there is no risk of resetting it in error when bit manipulation instructions are used. EN: Enable / Disable. 0 = DMA cell disabled. DMA INITIAL COUNTER REGISTER(ICTR) Address: 004C h -- Read / Write Reset condition: XXXX XXXX (XX h) The value of IADR, CADR, ICTR and CCTR are not affected when EN is reset. If the DMA is disabled when the DDC peripheral requests a DMA access, the DMA cell will simply transmit the request to the CPU using an interrupt line. The DMA request will then be serviced as an interrupt request. 1 = DMA cell enabled. Set and reset by software. ITE: Interrupt Enable 0 = Interrupt request disabled 1 = Interrupt request enabled. This 8-bit register contains the initial number of bytes to be transmitted before an autoreload occurs, or before an interrupt request is to be sent to the CPU. It is not affected by Reset or by disabling the DMA. Read accesses are always allowed. Write accesses are allowed only in SUSPEND MODE (SUSP bit "high"). DMA CURRENT COUNTER REGISTER(CCTR) Address: 004D h) -- Read / Write An interrupt is sent to the CPU when CCTR reaches 00 (MATCH-bit high). Set and reset by software. RW: Transfer Direction. 0 = From the DDC cell to memory. Reset condition: XXXX XXXX (XX h) This 8-bit register contains the number of byte to be transmitted before an autoreload occurs or before send an interrupt request to the CPU. It is not 82/119 1 = From memory to the DDC cell. Set and reset by software. 82 ST7272 DDC-DMA (Cont'd) DECR: Decrementing / Incrementing 1 = CADR will be decremented after each DMA transfer. 0 = CADR will be incremented after each DMA transfer. In both cases, CCTR is decremented after each DMA transfer, Set and reset by software. AUTOR: Auto Reload / Non Auto Reload 0 = At the end of a block transfer, when the CCTR reaches 00h, the DMA cell goes into Suspend mode (SUSP bit high), and if the ITE bit is set an interrupt is sent to the CPU just after the DMA transfer (MATCH bit high). It allows the received block to be procesed, or the preparation of the next block before initiating a new block transfer. Transfer is inhibited until the SUSP bit is reset by software. 1 = At the end of a block transfer, when the CCTR reaches 00h, the CADR is automatically reloaded with the IADR value, and the CCTR is reloaded with the ICTR value. The MATCH bit is set, but the transfer is not suspended (the SUSP bit remains "low"). Set and reset by software. SUSP: Suspend Mode 0 = The DMA cell is active. 1 = The DMA cell is in Suspend Mode. If a DMA request occurs when the DMA is in Suspend Mode, the request remains pending. It will be serviced as soon as SUSP goes "low". SUSP is set by software or when the CCTR reaches 00 in non-autoreload mode. SUSP is reset by software. Note: As the SUSP bit is set by the DMA when the CPU activity is stopped, there is no risk of reseting it in error when bit manipulation instructions are used. When IT-ERR is generated by the DDC peripheral, SUSP is set by hardware. 83/119 83 ST7272 5 SOFTWARE 5.1 ST7 ARCHITECTURE The 8-bit ST7 Core is designed for high code efficiency. It contains 6 internal registers, 17 main addressing modes and 63 instructions. The 6 internal registers include 2 index registers, an accumulator, a 16-bit Program Counter, a stack pointer and a condition code register. The two Index registers X and Y enable Indexed Addressing modes with or without offset, along with read-modify-write type data manipulations. These registers simplify branching routines and data modifications. The 16-bit Program Counter is able to address up to 64K of ROM /EPROM memory. The 6-bit Stack Pointer provides access to a 64-level Stack and an upgrade to an 8-bit Stack Pointer is foreseen in order to be able to manage a 256-level Stack. The Core also includes a Condition Code Register providing 5 Condition Flags that indicate the result of the last instruction executed. The 17 main Addressing modes, including Indirect Relative and Indexed addressing, allow sophisticated branching routines or CASE-type functions. The Indexed Indirect Addressing mode, for instance, permits look-up tables to be located anywhere in the address space, thus enabling very flexible programming and compact C-based code. The 63-instruction Instruction Set is 8-bit oriented with a 2-byte average instruction size. This Instruction Set offers, in addition to standard data movement and logic/arithmetic functions, byte multiplication, bit manipulation, data transfer between Stack and Accumulator (Push/Pop) with direct stack access, as well as data transfer using the X and Y registers. 5.2 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Inherent Immediate Direct Indexed Indirect Relative Bit operation Example nop ld A,#$55 ld A,$55 ld A,($55,X) ld A,([$55],X) jrne loop bset byte,#5 The ST7 Instruction set is designed to minimize the number of bytes required per instruction: To do so, most of the addressing modes may be subdivided in two sub-modes called long and short: - The long addressing mode is the most powerful because it can reach any byte in the 64kb addressing space, but the instruction is bigger and slower than the short addressing mode. - The short addressing mode is less powerful because it can generally only access page zero (0000 - 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions are only working with short addressing modes (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) Both modes have pros and cons, but the programmer does not need to choose which one is the best: the ST7 Assembler will always choose the best one. 84/119 84 ST7272 ST7 ADDRESSING MODES(Cont'd) Table 18. ST7 Addressing Mode Overview: Mode Inherent Immediate Short Long No Offset Short Long Short Long Short Long Relative Relative Bit Bit Bit Bit Direct Direct Direct Direct Direct Indirect Indirect Indirect Indirect Direct Indirect Direct Indirect Direct Indirect Relative Relative Indexed Indexed Indexed Indexed Indexed nop ld A,#$55 ld A,$10 ld A,$1000 ld A,(X) ld A,($10,X) ld A,($1000,X) ld A,[$10] ld A,[$10.w] ld A,([$10],X) ld A,([$10.w],X) jrne loop jrne [$10] bset $10,#7 bset [$10],#7 btjt $10,#7,skip btjt [$10],#7,skip 00..FF 0000..FFFF 00..FF 00..1FE 0000..FFFF 00..FF 0000..FFFF 00..1FE 0000..FFFF PC+/-127 PC+/-127 00..FF 00..FF 00..FF 00..FF 00..FF byte 00..FF byte 00..FF byte 00..FF 00..FF 00..FF 00..FF byte word byte word Syntax Destination Ptr addr Ptr size Lngth +0 +1 +1 +2 +0 +1 +2 +2 +3 +2 +3 +1 +2 +1 +2 +2 +3 85/119 85 ST7272 ST7 ADDRESSING MODES(Cont'd) Inherent: All related instructions are single byte ones. The op-code fully specify all required information for the CPU to process the operation. These instructions are single byte ones.: Inherent Instruction NOP TRAP WFI HALT RET IRET SIM RIM SCF RCF RSP LD CLR PUSH/POP INC/DEC TNZ CPL, NEG MUL SLL, SRL, SRA, RLC, RRC SWAP Function No operation S/W Interrupt Wait For Interrupt (Low Power Mode) Halt Oscillator (Lowest Power Mode) Sub-routine Return Interrupt Sub-routine Return Set Interrupt Mask Reset Interrupt Mask Set Carry Flag Reset Carry Flag Reset Stack Pointer Load Clear Push/Pop to/from the stack Increment/Decrement Test Negative or Zero 1 or 2 Complement Byte Multiplication Shift and Rotate Operations Swap Nibbles Direct (short, long): The data byte required to carry out the operation is found by its memory address, which follows the op-code. Available Long and Short Direct Instructions LD CP AND, OR, XOR ADC, ADD, SUB, SBC BCP Load Compare Logical Operations Arithmetic Additions/Substractions operations Bit Compare Function Short Direct Instructions Only CLR INC, DEC TNZ CPL, NEG BSET, BRES BTJT, BTJF SLL, SRL, SRA, RLC, RRC SWAP CALL, JP Clear Function Increment/Decrement Test Negative or Zero 1 or 2 Complement Bit Operations Bit Test and Jump Operations Shift and Rotate Operations Swap Nibbles Call or Jump subroutine Immediate: The required data byte to do the operation is following the op-code. These are two byte instructions, one for the op-code and the other one for the immediate data byte. Immediate Instruction LD CP BCP AND, OR, XOR ADC, ADD, SUB, SBC Load Compare Bit Compare Logical Operations Arithmetic Operations Function The direct addressing mode consists of two submodes: Direct (short): The address is a byte, thus require only one byte after the op-code, but only allow 00..FF addressing space. Direct (long): The address is a word, thus allowing 64Kb addressing space, but requires 2 bytes after the opcode. 86/119 86 ST7272 ST7 ADDRESSING MODES(Cont'd) Indexed (no offset, short, long) The required data byte to do the operation is found by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset which follows the op-code. The offset is a word, thus allowing 64Kb addressing space, but requires 2 bytes after the op-code. Indirect (short, long): The required data byte to do the operation is found by its memory address, located in memory (pointer). No Offset, Long and Short Indexed Instruc. LD CP AND, OR, XOR ADC, ADD, SUB, SBC BCP Load Function Available Long and Short Indirect Instructions LD CP AND, OR, XOR ADC, ADD, SUB, SBC BCP Load Compare Logical Operations Arithmetic Additions/Substractions operations Bit Compare Function Compare Logical Operations Arithmetic Additions/Substractions operations Bit Compare No Offset and Short Indexed Inst. Only CLR INC, DEC TNZ CPL, NEG BSET, BRES BTJT, BTJF SLL, SRL, SRA, RLC, RRC SWAP CALL, JP Clear Function Short Indirect Instructions Only CLR INC, DEC TNZ CPL, NEG BSET, BRES BTJT, BTJF SLL, SRL, SRA, RLC, RRC SWAP CALL, JP Clear Increment/Decrement Test Negative or Zero 1 or 2 Complement Bit Operations Bit Test and Jump Operations Shift and Rotate Operations Swap Nibbles Call or Jump subroutine Function Increment/Decrement Test Negative or Zero 1 or 2 Complement Bit Operations Bit Test and Jump Operations Shift and Rotate Operations Swap Nibbles Call or Jump subroutine The indirect addressing mode consists of three sub-modes: Indexed (no offset): There is no offset, (no extra byte after the opcode), but only allows 00.FF addressing space. Indexed (short): The offset is a byte, thus require only one byte after the op-code, but only allow 00..1FE addressing space. Indexed (long): The pointer address follows the op-code. The indirect addressing mode consists of two sub-modes: Indirect (short): The pointer address is a byte, the pointer size is a byte, thus allowing 00..FF addressing space, and requires 1 byte after the op-code. Indirect (long): The pointer address is a byte, the pointer size is a word, thus allowing 64Kb addressing space, and requires 1 byte after the op-code. 87/119 87 ST7272 ST7 ADDRESSING MODES(Cont'd) Indirect Indexed (short, long): This is a combination of indirect and short indexed addressing mode. The required data byte to do the operation is found by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the op-code. The indirect indexed addressing mode consists of two sub-modes: Indirect Indexed (short): The pointer address is a byte, the pointer size is a byte, thus allowing 00..1FE addressing space, and requires 1 byte after the op-code. Long and Short Indirect Indexed Instructions LD CP AND, OR, XOR ADC, ADD, SUB, SBC BCP Load Indirect Indexed (long): Function The pointer address is a byte, the pointer size is a word, thus allowing 64Kb addressing space, and requires 1 byte after the op-code. Compare Logical Operations Arithmetic Additions/Substractions operations Bit Compare Relative mode (direct, indirect): This addressing mode is used to modify the PC register value, by adding an 8 bit signed offset to it. Available Relative Direct/Indirect Instructions Function Conditional Jump Call Relative Short Indirect Indexed Instructions Only CLR INC, DEC TNZ CPL, NEG BSET, BRES BTJT, BTJF SLL, SRL, SRA, RLC, RRC SWAP CALL, JP Clear Function JRxx CALLR Increment/Decrement Test Negative or Zero 1 or 2 Complement Bit Operations Bit Test and Jump Operations Shift and Rotate Operations Swap Nibbles Call or Jump subroutine The relative addressing mode consists of two submodes: Relative (direct): The offset is following the op-code. Relative (indirect): The offset is defined in memory, which address follows the op-code. 88/119 88 ST7272 5.3 ST7 INSTRUCTION SET The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations Shift and Rotates Unconditional Jump or Call Conditional Branch Interruption management Code Condition Flag modification LD PUSH INC CP AND BSET BTJT ADC SLL JRA JRxx TRAP SIM WFI RIM HALT SCF IRET RCF CLR POP DEC TNZ OR BRES BTJF ADD SRL JRT SUB SRA JRF SBC RLC JP MUL RRC CALL SWAP CALLR SLA NOP RET BCP XOR CPL NEG RSP be subdivided into 13 main groups as illustrated in the following table: Using a pre-byte The instructions are described with one to four opcodes. In order to extend the number of available opcodes for an 8-bit CPU (256 op-codes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede. The whole instruction becomes: PC-2 PC-1 PC End of previous instruction Prebyte Op-code PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one. 89/119 89 ST7272 Mnemo ADC ADD AND BCP BRES BSET BTJF BTJT CALL CALLR CLR CP CPL DEC HALT IRET INC JP JRA JRT JRF JRIH JRIL JRH JRNH JRM JRNM JRMI JRPL JREQ JRNE JRC JRNC JRULT JRUGE JRUGT JRULE Description Add with Carry Addition Logical And Bit compare A, Memory Bit Reset Bit Set Jump if bit is false (0) Jump if bit is true (1) Call subroutine Call subroutine relative Clear Arithmetic Compare One Complement Decrement Halt Interrupt routine return Increment Absolute Jump Jump relative always Jump relative Never jump Jump if Port B INT pin = 1 Jump if Port B INT pin = 0 Jump if H = 1 Jump if H = 0 Jump if I = 1 Jump if I = 0 Jump if N = 1 (minus) Jump if N = 0 (plus) Jump if Z = 1 (equal) Jump if Z = 0 (not equal) Jump if C = 1 Jump if C = 0 Jump if C = 1 Jump if C = 0 Jump if (C + Z = 0) Jump if (C + Z = 1) Function/Example A =A+M+C A =A+M A =A.M tst (A . M) bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1 A A A A M M M M Dst Src M M M M H H H I N N N N N Z Z Z Z Z C C C C C reg, M tst(Reg - M) A = FFH-A dec Y reg reg, M reg, M 0 Pop CC, A, X, PC inc X jp [TBL.w] reg, M H I M 0 N N N 1 Z Z Z C 1 N N Z Z C jrf * (no Port B Interrupts) (Port B interrupt) H=1? H=0? I =1? I =0? N=1? N=0? Z=1? Z=0? C=1? C=0? Unsigned < Jmp if unsigned >= Unsigned > Unsigned <= 90/119 90 ST7272 Mnemo LD MUL NEG NOP OR POP Load Description Function/Example dst <= src X,A = X * A neg $10 Dst reg, M A, X, Y reg, M Src M, reg X, Y, A H I N N Z Z C Multiply Negate (2's compl) No Operation OR operation Pop from the Stack 0 N Z 0 C A =A+M pop reg pop CC A reg CC M M M M reg, CC H I N N Z Z C PUSH RCF RET RIM RLC RRC RSP SBC SCF SIM SLA SLL SRL SRA SUB SWAP TNZ TRAP WFI XOR Push onto the Stack Reset carry flag Subroutine Return Enable Interrupts Rotate left true C Rotate right true C Reset Stack Pointer Substract with Carry Set carry flag Disable Interrupts Shift left Arithmetic Shift left Logic Shift right Logic Shift right Arithmetic Substraction SWAP nibbles Test for Neg & Zero S/W trap Wait for Interrupt Exclusive OR push Y C=0 0 I =0 C <= A <= C C => A => C S = Max allowed A =A-M-C C=1 I =1 C <= A <= 0 C <= A <= 0 0 => A => C A7 => A => C A =A-M A7-A4 <=> A3-A0 tnz lbl1 S/W interrupt reg, M reg, M reg, M reg, M A reg, M M A M reg, M reg, M 0 N N Z Z C C N Z C 1 1 N N 0 N N N N 1 0 Z Z Z Z Z Z Z C C C C C A = A XOR M A M N Z 91/119 91 ST7272 6 ELECTRICAL CHARACTERISTICS 6.1 ABSOLUTE MAXIMUM RATINGS Devices of the ST72 family contain circuitry to protect the inputs against damage due to high static voltage or electric fields. Nevertheless, it is recommended that normal precautions be observed in order to avoid subjecting this high-impedance circuit to voltages above those quoted in the Absolute Maximum Ratings. For proper operation, it is recommended that VIN and VOUT be constrained within the range: VSS VIN and VOUT VDD To enhance reliability of operation, it is recommended to configure unused I/Os as inputs and to connect them to an appropriate logic voltage level such as VSS or VDD. All the voltage in the following tables are referenced to VSS. Stresses above those listed as "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 19. Absolute Maximum Ratings (Voltage Referenced to V ). SS Symbol VDD VDDA VIN VOUT IIN IOUT TA TSTG PD ESD Ratings Recommended Supply Voltage Analog Reference Voltage Input Voltage Output Voltage Input Current Output Current Operating Temperature Range Storage Temperature Range Power Dissipation ESD susceptibility Value -0.3 to +6.0 -0.3 to +9.0 VSS -0.3 to VDD + 0.3 VSS -0.3 to VDD + 0.3 -10...... +10 -10...... +10 0 to +70 -65 to +150 TBA 2000 Unit V V V V mA mA OC OC mW V Note: The maximum accumulated current off all I/O pins should not exceed 40 mA for VDD and 40 mA for VSS. 92/119 92 ST7272 6.2 POWER CONSIDERATIONS The average chip-junction temperature, T , in deJ grees Celsius, may be calculated using the following equation: TJ = TA + (PD x JA) (1) Therefore: Where: - TA is the Ambient Temperature inC, - JA is the Package Junction-to-Ambient Thermal Resistance, in C/W, - PD is the sum of PINT and PI/O, - PINT is the product of IDD and VDD, expressed in Watts. This is the Chip Internal Power - PI/O represents the Power Dissipation on Input and Output Pins; User Determined. For most applications PI/O An approximate relationship between P and TJ D (if PI/O is neglected) is given by: PD = K/ (TJ + 273C) (2) K = PD x (TA + 273C) + JA x PD2 (3) Where: - K is a constant for the particular part, which may be determined from equation (3) by measuring PD (at equilibrium) for a known T Using this valA. ue of K, the values of PD and TJ may be obtained by solving equations (1) and (2) iteratively for any value of TA. JA 93/119 93 ST7272 6.3 DC ELECTRICAL CHARACTERISTICS (TA = 0 to +70C unless otherwise specified Symbol VDD V OL V OL V OL V OL V OL VOH VIH VIL Parameter Supply Voltage Output Voltage Low Port A (Open drain) Output Voltage Low Port B (0-7), Port D(0:7) Push-pull Output Voltage Low Port C (PC2,PC3,PC4) Push-pull Output Voltage Low Port C (PC0,PC1,PC5) Open drain during Power ON Reset and Watchdog Reset Output Voltage High Push-pull Input High Voltage PA(0-7), PB(0-7), PC(0-5), PD(0-4), RESET Input Low Voltage PA(0-7), PB(0-7), PC(0-5), PD(0-4), RESET I/O Ports Hi-Z Leakage Current PA(0-7), PB(0-7), PC(0-5), PD(0-4), RESET COUT CIN RON IRPU Capacitance: Ports (as Input or Output), RESET DA1,D(A3-17)(PWM/BRM) Serial Resistor Pull-up resistor current VDD=5v VIN=VSS 700 20 IOH =1.6 mA Leading Edge Trailing Edge VSS 10 VDD 12 8 1000 uA pF pF Ohms uA VDD-0.8 0.7xV DD V SS VDD 0.3xV DD IOL=1.6 mA Test Condit ions Value min 4.5 typ max 5.5 0.4 Unit V V V V V V V V V uA IOL=1.6 mA IOL=1.6 mA IOL=1.6 mA 0.4 0.4 0.4 0.4 IIL 94/119 94 ST7272 DC ELECTRICAL CHARACTERISTICS(Cont'd) DDC Bus (I2C INTERFACE) Symbol Parameter Hysteress of Shmitt trigger inputs VHYS TSP TOF fixed input levels VDD-related input levels Pulse width of spikes which must be suppressed by the input filter Output fall time from VIHmin to VILmax with a bus capacitance from 10 pF to 400pF with up 3mA sink current at VOL1 I C Input current each I/O pin with an input voltage between 0.4v and 0.9 VDD max Capacitive load for each I/O pin -10 250 10 10 A pF ns na na na na na na ns V Min Max Unit A/D CONVERTER Symbol Val Terr Tcon Rva Parameter Resolution Total Error Conversion Time Analog Source Impedance Test Conditions FOSC = 8 MHz FOSC = 8 MHz FOSC = 8 MHz 16 30 Min Typ 8 3 Max Unit bit LSB s K 95/119 95 ST7272 6.4 AC ELECTRICAL CHARACTERISTICS (TA = 0 to +70C unless otherwise specified) Symbol V DD Parameter Operating Supply Voltage Test Condition s 4 MHz Internal RUN Mode Fext = 8MHz IDD Supply Current VDD = 5.0V WAIT Mode fext = 8MHz VDD = 5.5V 3.5 5 mA Value Min 4.5 7.5 Typ. Max 5.5 10 Unit V mA 6.5 CONTROL TIMING (Operating conditions TA 0 to +70C unless otherwise specified) Symbol fOSC tILCH tRL tPORL TDOGL tDOG tILIL tOXOV tDDR Parameter Frequency of Operation Halt Mode Recovery Startup Time External RESET Input pulse Width Power Reset Duration Watchdog RESET Output Pulse Width Watchdog Time-out Interrupt Pulse Period Crystal Oscillator Start-up Time Power up rise time VDD min 1.5 4096 2 49,152 (1) 50 100 2 3,145,728 Test Condition s VDD = 4.5V f external f internal Value Min Typ. Max 8 4 20 Unit MHz ms tCYC tCYC tCYC tCYC tCYC ms ms Notes : 1. The minimum period tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 cycles. 96/119 96 ST7272 AC ELECTRICAL CHARACTERISTICS(Cont'd) 6.5.1 DDC (I2C BUS) Interface 6.5.1.1 Timing Parameter Bus free time between a STOP and START condition Hold time START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Capacitive load for each bus line 4.0 400 Min 4.7 4.0 4.7 4.0 4.7 250 (1) 250 1000 300 Max Symbol Tubs Thd:sta Tlow Thigh Tsu:sta Thd:dat Tsu:dat Tr Tf Tsu:sto Cb Unit ms s s s s ns ns ns ns ns pF 1. The device provides a hold time of at least 250ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. Cb = total capacitance of one bus line in pF Figure 45. Definition of Timing Terminology SDA Tbuf SCL Tlow Tr Tf Thd:sta Tsp Thd:sta Thd:dat Thigh Tsu:dat Tsu:sta Tsu:sto 97/119 97 ST7272 7 GENERAL INFORMATION 7.1 PACKAGE MECHANICAL DATA Figure 46. 56 Shrink Plastic Dual In Line Package, 600-mil Width Dim A A1 B B1 C D D1 E E1 K1 K2 L e1 2.54 1.78 13.72 0.070 0.51 0.35 0.75 0.20 52.12 18.54 mm Min Typ Max 5.08 0.020 0.59 0.014 1.42 0.030 0.36 0.008 2.052 0.730 0.540 0.150 0.023 0.056 0.014 Min inches Typ Max 0.200 3.81 0.100 Number of Pins N 56 7.2 ORDERING INFORMATION 7.2.1 Introduction The following section describes the approved procedure for transfer of User Program/Data ROM Code to SGS-THOMSON Microelectronics as well as the basis for contractual agreement with respect to mask programmed devices. 7.2.2 Communication of the User ROM Code To formally communicate the desired Program/Data ROM contents to SGS-THOMSON Microelectronics, the following must be supplied: - a file in MOTOROLA S19 FORMAT (on diskette, via electronic mail or by BBS); - a correctly completed and signed Option List form as shown overleaf. The User Code must respect the ROM Memory Map for the selected device option. Table 21. Ordering Information Sales Types ST 7272N5B1 ROM Size 24K RAM Size 384 Temperature Range 0 to +70C Package PSDIP56 The User Code must be generated using an approved ST7 assembler. All unused memory locations shall be set to FF h. 7.2.3 Verification and Formal Approval When SGS-THOMSON Microelectronics receives the User Code file, it will return a copy of the processed file to the Customer. The Customer will then send formal notification to SGS-THOMSON Microelectronics, approving the file contents. This statement and the file copies to which it refers will then form the basis of the contractual agreement between the Customer and SGS-THOMSON Microelectronics and the agreed file will be used to produce the mask for the programmed MCU device. The SGS-THOMSON Sales Organization will be pleased to provide detailed information relating to the above technical and contractual points. 98/119 98 ST7272 ST7272 MICROCONTROLLER OPTION LIST Customer Address . .. ... . . .. . . .. .. .. . . .. . .. . .. . ... .. . . .. . ... . .. . . . ... . . .. . . .. . .. .. . . .. ... . . .. . . .. .. .. . . .. . .. . .. . ... .. . . .. . ... . .. . . . ... . . .. . . .. . .. .. . . .. . . . ... . .. ... . . .. .. . . .. . .. . .. . .. .. . . .. . .. . . ... . .. ... ... .. .. . .. . Contact Phone No . .. ... . . .. . . .. .. .. . . .. . .. . .. . ... .. . . .. . ... . .. . . . ... . . .. . . .. . .. .. . . .. ... . . .. . . .. .. .. . . .. . .. . .. . ... .. . . .. . ... . .. . . . ... . . .. . . .. . .. .. . Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SGS-THOMSON Microelectronics references Device: [] ST7272 24K ROM Package: [ ] SDIP56 Temperature Range: [ ] 0C to + 70C Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ _ " Clamping Output Option: [ ] Maximum delay 250ns Programmable back porch clamping width (0, 250ns, 500ns, 1 us) [ ] Maximum delay 125ns Programmable back porch clamping width (0, 125ns, 250ns, 500 us) All options must be defined before acceptance Signature Date 99/119 99 ST72E72 - ST72T72 Notes: 100/119 100 ST72E72 ST72T72 8-BIT MCU WITH 24K EPROM, EEPROM, ADC, PWM/BRM DACs, SYNC PROCESSOR, EWPCC, TIMER AND DDC I/F PRELIMINARY DATA s s s s s s s s s s s s s s s s s s s s s s s s s s 4.5V to 5.5V Supply Operating Range 8MHz Maximum Oscillator Frequency Fully Static operation 0C to + 70C Operating Temperature Range Run, Wait, Halt, and RAM Retention modes User EPROM/OTP: 24Kbytes Data RAM: 384 bytes EEPROM: 640 + 256 bytes 56 pin Shrink Dual-in-Line package 27 multifunctional bidirectional I/O lines: - 8 lines with 12V open-drain drive capability - 8 Programmable Interrupt inputs - 8 Analog inputs 16-bit Timer, featuring: - 2 Input Captures - 2 Output Compares (1 output pin) 8-bit Analog-to-Digital converter Programmable Watchdog Timer 16 10-bit PWM/BRM Digital to Analog outputs 2 12-bit PWM/BRM Digital to Analog outputs EWPCC circuit with on-chip EEPROM New upgraded Sync processor for Mode Recognition, Power Management and Composite Video Blanking Generator DDC 1/2/AB interface with built-in DMA and 2C I Master/Slave Modes Master Reset and Power-On Reset 8-bit Data Manipulation 63 Basic Instructions 17 main Addressing Modes 8 x 8 Unsigned Multiply Instruction True Bit Manipulation Complete Development Support on PC/DOS Real-Time Emulator Full Software Package (C-Compiler, CrossAssembler, Debugger) PSDIP56 CSDIP56 May 1996 This is advance information from SGS-TH OMSON. Details are subject tochange without notice. 101/119 101 ST72E72 - ST72T72 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST72T72 and the ST72E72 devices are OTP and EPROM versions respectively of the ST7272 ROM based HCMOS Microcontroller Unit. Please refer to the ST7272 ROM device Datasheet for further details. From the user's point of view, both the OTP and EPROM devices are functionally identical to the ROM device and possess the same software and hardware features. An additional mode is available Figure 1. ST72E72/T72 Block Diagram 24 KBytes (1) ROM PORT A PA0-PA7 to allow programming of the EPROM user memory array. This is set by a specific voltage applied to the VPP/Test pin. The EPROM and OTP devices feature 24K of user programmable EPROM memory; the EPROM device features a windowed ceramic package which allows the contents of the memory array to be erased by exposure to UV light. EWPCC EEPROM 256 Bytes EWPCC VFBACK PORT B ADC V DDA V SSA EWPCC PB0-PB7 AIN0-AIN7 WAKE-UP INTERRUPT VFBACK (PB0) Ain0-Ain7 RAM 384 Bytes ADDRESS / DATA BUSES DDC (12C) MOSI MISO EEPROM 640 Bytes PORT C CMP0 TIMER H/CSYNC HSYNCI2 PC0-PC5 (PC5) (PC4) SDA1/TX (PC3) SCL1/RX (PC2) HSYNCI2 (PC1) OCMP/HFBAC (PC0) K RESET WATCHDOG CONTROL 8-BIT CORE ALU SYNC PROCESSOR VSYNC SCK SS HSYNCI1 VSYNCI1 PD0-PD4 CSYNCI (PD0) HSYNCO (PD1) VSYNCO (PD2) CLMPO (PD3) VSYNCI2 (PD4) DA0,DA1 12-Bit D/A DA2,DA17 10-Bit D/A PCL PCH SP X Y A CC VSYNCI2 CSYNCI HSYNCO VSYNCO POWER SUPPLY OSC. INTERNAL CLOCK PORT D PWM/BRM VDD V SS OSCin OSCout CLMPO VR02069A Note1: EPROM/OTP 102/119 1 ST72E72 - ST72T72 1.2 PIN DESCRIPTION VDD Power supply VSS Digital Ground VDDA Analog VDD and reference for EWPCC Digital to Analog Converter (typically 8 Volts). VSSA Analog VSS for EWPCC DAC. OSCin, OSCout Oscillator input and output pins; usually connected to a parallel resonant crystal or ceramic resonator. Altenatively an external clock source may also be input via OSCin. EWPCC Analog correction signal output from East-West Pin Cushion Correction circuit. SCL1/RX DDC Serial Clock or RX (Falling edge detector with interrupt). SDA1/TX DDC Serial Data or TX. OCMP / HFBACK Output compare signal from the Timer. HSYNCI1 Horizontal Synchronization Input 1. VSYNCI1 Vertical Synchronization Input 1. HSYNCI2 Sync Processor Horizontal or complete Synchronization Input 2. VSYNCI2 Vertical Synchronization Input 2. CSYNCI Composite Synchronization Input. This pin accepts the composite synchronization input when the Sync Processor I/O functions are enabled. VFBACK Vertical Flyback signal used for timing correlation for the East-West Pin Cushion correction. HFBACK Horizontal Flyback Input. BLANK OUT Video Blanking Output. HSYNCO Horizontal Synchronization Output from the Sync Processor. VSYNCO Vertical Synchronization Output from the Sync Processor. CLMPO Clamp Output. This pin outputs the clamping (back porch) output signal from the Sync Processor . DA0, DA1 12-bit PWM/BRM outputs (for Analog Controls, after external filtering). DA2-DA17 10-bit PWM/BRM outputs (for Analog controls, after external filtering). PORT A 8 I/O lines, bit programmable, accessed through PADDR and PADR Registers. Each bit can be defined as a standard input port bit without pull-up resistor or as an open drain output port (up to 12V). CAUTION: The VPP/TEST pin MUST be connected directly to the VSS pin on the device in order to ensure correct operation. PORT B 8 Standard bit-programmable I/O lines accessed through the PBDDR and PBDR Registers. Each bit can be programmed as an analog input (by control bits in the PORT B Configuration register), digital input (with internal pull-up resistor), push-pull digital output or as interrupt wakeup (with pull-up). These negative edge or low-level sensitive interrupt lines can wake-up the MCU from WAIT or HALT mode. PB0 is used for the East-West Pin cushion controller VFBACK input when the EWPCC is used. PORT C 6 Standard bit-programmable I/O lines accessed through the PCDDR and PCDR Registers. PC 0,1 are Inputs with Pull-Up or Push-Pull Outputs, PC 2,3 are Open Drain outputs or Inputs without Pull-Up, PC 4,5 are Open Drain outputs or Digital Inputs with or without Pull-Up internal resistor. The pull-up resistor is enabled for all bits by one control bit in the Programmable Input/Output Configuration Register. PC0 can also be configured as Timer Output Compare pin or Horizontal Flyback Input. PC1 can be programmed as HSYNCI2 sync input for the Sync Processor. PC2/SCL1 and PC3/SDA1 are alternate functions with the DDC cell. PORT D 5 Standard bit-programmable I/O lines accessed through PDDDR and PDDR Registers. Each bit can be programmed as an input (with internal pull-up resistor), push-pull output or Synchronization inputs and outputs to/from the Sync Processor. When programmed as inputs, Video Synchronization signals can be directly inspected. The inputs may also be passed through the Sync Processor to the Timer Input Captures. RESET An active-low signal on this pin forces initialization of the MCU. This is the top priority non maskable interrupt. This pin is driven low if the Watchdog Timer has been triggered. The resulting pulse can be used to reset external peripherals. VPP/TEST This pin must be held low for normal operation. In programing mode, this pin is connected to VPP. 103/119 1 ST72E72 - ST72T72 PIN DESCRIPTION (Cont'd) The following table describes basic and alternate functions for each pin. Relevant ancillary information is given in the Remarks column. The pin configuration is illustrated for convenience. ST7272 Pin Configuration 1 2 3 56 55 54 26 27 28 31 30 29 VR01740A Pin Name(s) V DDA EWPCC DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 / VFBACK PD4 / VSYNCI2 PD3 / CLMPO DA10 DA11 Basic Function Analog power supply EWPCC circuit analog output 12-bit DAC PWM outputs Alternate Function -- Pin 1 2 3 4 5 6 7 Typically +8V 2 - 6V Remarks 10-bit DAC PWM outputs -- 8 9 10 11 12 13 14 15 Generated by PWM/BRM circuitry, need external filtering. Analog input Port B I/Os 16 17 18 19 Standard I/O or alternate function. The I/O configuration is software programmable as input with pull-ups, wake-up interrupt input, or pushpull output. Analog input or VFBACK Port D I/O Port D I/O 10-bit DAC PWM outputs VSYNCI2 CLMPO - 20 As above, or input for EWPCC circuit, when active. Vertical Sync input 2 (TTL with pull-up). Clamp output from Sync circuit. Generated by PWM/BRM circuitry, need external filtering. 21 22 23 24 104/119 102 ST72E72 - ST72T72 PIN DESCRIPTION (Cont'd) The following table describes basic and alternate functions for each pin. Relevant ancillary information is given in the Remarks column. The pin configuration is illustrated for convenience. ST7272 Pin Configuration 1 2 3 56 55 54 26 27 28 31 30 29 VR01740A Pin Name(s) Basic Function General reset input and output Alternate Function Pin Remarks As an input, a Reset is generated by an active low signal; when the Watchdog has triggered this pin will be driven low to reset external peripherals. Vertical Sync output from Sync processor. Vertical Sync input to Sync processor (TTL with pull-up). 4.5 - 5.5V Horizontal Sync input to Sync processor (TTL with pull-up). Horizontal Sync output from Sync processor. Composite Sync input (TTL with pull-up). These pins may be connected to a parallel resonant crystal or ceramic resonator; alternatively an external clock source may be connected to OSCIN. Generated by PWM/BRM circuitry, need external filtering. Video blanking output from Sync processor. RESET - 25 PD2 / VSYNCO VSYNCI1 V DD HSYNCI1 PD1 / HSYNCO PD0 / CSYNCI OSCOUT OSCIN DA12 DA13 PA7 / BLANKOUT PA6 PA5 PA4 PA3 PA2 PA1 PA0 Port D I/O VSYNCI1 Power supply to digital circuits. HSYNCI1 VSYNCO 26 27 - 28 29 HSYNCO Port D I/Os CSYNCI Oscillator output Oscillator input 10-bit DAC PWM outputs - 30 31 32 33 34 35 36 37 38 39 BLANKOUT Port A I/Os - 40 41 42 43 Standard I/Os, bit programmable via PADDR and PADR registers as inputs without pull-ups or as open-drain outputs (up to 12V). 105/119 103 ST72E72 - ST72T72 PIN DESCRIPTION (Cont'd) The following table describes basic and alternate functions for each pin. Relevant ancillary information is given in the Remarks column. The pin configuration is illustrated for convenience. ST7272 Pin Configuration 1 2 3 56 55 54 26 27 28 31 30 29 VR01740A Pin Name(s) DA14 DA15 DA16 DA17 Basic Function 10-bit DAC PWM outputs Alternate Function Pin 44 45 46 47 Remarks Generated by PWM/BRM circuitry, need external filtering. This pin is for SGS-THOMSON internal use only and MUST be tied directly to VSS for normal operation. In programing mode this pin is connected to VPP. Output compare from Timer peripheral. or Horizontal flyback input (TTL with pull-up). Horizontal Sync input to Sync processor (TTL with pull-up). DDC serial clock. Can generate interrupt on falling edge for RX Start detection for software SCI. DDC serial data. OCMP can generate interrupt for TX bit timing for software SCI. - VPP/TEST PC0 / OCMP / HFBACK PC1 / HSYNCI2 PC2 / SCL1 / RX PC3 / SDA1 / TX PC4 PC5 V SS V SSA TEST VPP OCMP or HFBACK HSYNCI2 SCL1 48 49 50 Port C I/Os RX 51 SDA1 TX Digital Ground Analog Ground - 52 53 54 55 56 106/119 104 ST72E72 - ST72T72 1.3 MEMORY MAP Table 1. ST7272 Memory Map Add 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h PWM/B RM TIM EEP EW DACR PCC0 PCC1 CR0 CR1 CR2 CR3 CR SR IC1HR IC1LR OC1HR OC1LR CNTHR CNTLR ACNTHR ACNTLR IC2HR IC2LR OC2HR OC2LR PWM0 BRM0 PWM1 BRM1 ADC Block name Block Register mnemonic PADR PBDR PCDR PDDR PADDR PBDDR PCDDR PDDDR DR CR Register name Port A Data Register Port B Data Register Port C Data Register Port D Data Register Port A Data Direction Register Port B Data Direction Register Port C Data Direction Register Port D Data Direction Register ADC Data Register ADC control/Status register Reserved East/West DAC Register East/West Control 0 East/West Control 1 DDC EEPROM Control register GP1 EEPROM Control register GP2 EEPROM Control register E/W EEPROM Control register TIMER Control Register TIMER Status Register TIMER Input Capture High Register 1 TIMER Input Capture Low Register 1 TIMER Output Compare High Register 1 TIMER Output Compare Low Register 1 TIMER Counter High Register TIMER Counter Low Register TIMER Alternate Counter High Register TIMER Alternate Counter Low Register TIMER Input Capture High Register 2 TIMER Input Capture Low Register 2 TIMER Output Compare High Register 2 TIMER Output Compare Low Register 2 (12-BIT PWM) Register (12-BIT BRM) Register (12-BIT PWM) Register (12-BIT BRM) Register 00h 00h C0h 00h 00h 00h 00h 00h XXh XXh XXh XXh XXh FFh FCh FFh FCh XXh XXh XXh XXh 80h C0h 80h C0h R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register Read Only Register Read only Read only R/W Register R/W Register Read only R/W Register Read only R/W Register Read only Read only R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register Reset Status XXh XXh XXh XXh 00h 00h 00h 00h XX 00h Remarks R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register Read Only Register R/W Register 107/119 105 ST72E72 - ST72T72 Add 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h Block name Block Register mnemonic PWM2 BRM3 + BRM2 PWM3 PWM4 BRM5+ BRM4 PWM5 PWM6 BRM7 + BRM6 PWM7 PWM8 BRM9+ BRM8 Register name Reset Status 80h 00h 80h 80h 00h 80h 80h 00h 80h 80h 00h 80h 80h 00h 80h 80h 00h 80h 80h 00h 80h 80h 00h 80h Remarks PWM/B RM PWM9 PWM10 BRM11 + BRM10 PWM11 PWM12 BRM13+ BRM12 PWM13 PWM14 BRM15 + BRM14 PWM15 PWM16 BRM17+ BRM16 PWM17 PBICFGR PIOCFGR WDOGR MISCR CFGR MCR CCR POLR LATR HGENR VGENR ENR 10-BIT PWM/BRM Registers R/W Registers Port B Input Pull-Up Configuration Register Programmable I/O Configuration Register Watchdog Register Miscellaneous Register SYNCHRO Configuration Register SYNCHRO Multiplexer Register SYNCHRO Counter Register SYNCHRO Polarity Register SYNCHRO Latch Register SYNCHRO H Sync Generator Register SYNCHRO V Sync Generator Register SYNCHRO Processor Enable Register 00h F8h 7Fh 2Ah 00h 00h 00h 00h 00h 00h 00h 00h R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register SYNC 108/119 106 ST72E72 - ST72T72 Add 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059to 005Ah to 007Fh 0080h to 01BFh 01C0h to 01FFh 0200h to 027Fh 0280h to 02FFh 0300h to 03FFh 0400h to 04FFh 0500h to 05FFh Block name Block Register mnemonic IADHR IADLR CADHR Register name DMA Initial High Address Register DMA Initial Low Address Register DMA current High Address Register DMA current Low Address Register DMA Initial Counter Register DMA current Counter Register DMA Control Register Reserved DDC Control Register DDC 1st Status Register DDC 2nd Status Register DDC Clock Control Register DDC 7 Bits Slave address Register Reserved DDC Data Register Reserved CRC Low register / Reserved CRC High register/ Reserved Reserved Reset Status XXh XXh XXh XXh XXh XXh 00h Remarks R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register R/W Register Read only Read only R/W Register R/W Register R/W Register DMA CADLR ICTR CCTR CTLR CR SR1 SR2 CCR OAR1 DR CRCL CRCH 00h 00h 00h 00h 00h 00h DDC CRC ST INTERNAL USE ONLY User RAM 384 bytes, including stack Stack 64bytes Reserved DDC-EEPROM 128 bytes dedicated for DDC EEPROM GP1-EEPROM 256 bytes for Data GP1 EEPROM EEPROM 896 bytes in 4 banks GP2-EEPROM 256 bytes for Data GP2 EEPROM EWPCC-EEPROM 256 bytes for either EWPCC or Data GP3 EEPROM 109/119 107 ST72E72 - ST72T72 Add 0600h to 07FFh 0800h to 08FFh 0900h to 13FFh 1400h to 1FFFh 2000h to 7EFFh 7F00h to 7FEFh Block name Block Register mnemonic Register name Reset Status Remarks Unused Reserved Unused Reserved 24K bytes program EPROM/OTP Reserved 7FF0-7FF1 7FF2-7FF3 DDC/DMA (OR wiring) TIMER Overflow TOF TIMER Output compare OCMP TIMER Input capture ICAP RX falling edge Keyboard (PORT B) TRAP (software) RESET vector Internal Interrupts " " " " External Interrupts " CPU Interrupt 7FF0h to 7FFFh 7FF4-7FF5 7FF6-7FF7 7FF8-7FF9 7FFA-7FFB 7FFC-7FFD 7FFE-7FFF7 1.4 EPROM ERASURE The EPROM memory on the ST72E72 device is erased by exposure to high intensity UV light admitted through the transparent window. This exposure discharges the floating gate to its initial state through induced photo current. It is recommended that the device be kept out of direct sunlight, since the UV content of sunlight can be sufficient to cause functional failure. Extended exposure to room level fluorescent lighting may also cause erasure. An opaque coating (paint, tape, label, etc...) should be placed over the package window if the product is to be operated under these lighting conditions. Covering the window also reduces IDD in power-saving modes due to photo-diode leakage currents. An Ultraviolet source of wave length 2537 A yielding a total integrated dosage of 15 Watt-sec/cm is required to erase the device. The device will be erased in 15 to 20 minutes if such a UV lamp with a 12mW/cm power rating is placed 1 inch from the device window without any interposed filters. 110/119 108 ST72E72 - ST72T72 2 ELECTRICAL CHARACTERISTICS 2.1 ABSOLUTE MAXIMUM RATINGS Devices of the ST72 family contain circuitry to protect the inputs against damage due to high static voltage or electric fields. Nevertheless, it is recommended that normal precautions be observed in order to avoid subjecting this high-impedance circuit to voltages above those quoted in the Absolute Maximum Ratings. For proper operation, it is recommended that VIN and VOUT be constrained within the range: VSS VIN and VOUT VDD To enhance reliability of operation, it is recommended to configure unused I/Os as inputs and to connect them to an appropriate logic voltage level such as VSS or VDD. All the voltage in the following tables are referenced to VSS. Stresses above those listed as "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings (Voltage Referenced to V ). SS Symbol VDD VDDA VIN VOUT IIN IOUT TA TSTG PD ESD Ratings Recommended Supply Voltage Analog Reference Voltage Input Voltage Output Voltage Input Current Output Current Operating Temperature Range Storage Temperature Range Power Dissipation ESD susceptibility Value -0.3 to +6.0 -0.3 to +9.0 VSS -0.3 to VDD + 0.3 VSS -0.3 to VDD + 0.3 -10...... +10 -10...... +10 0 to +70 -65 to +150 TBA 2000 Unit V V V V mA mA OC OC mW V Note: The maximum accumulated current off all I/O pins should not exceed 40 mA for VDD and 40 mA for VSS. 111/119 109 ST72E72 - ST72T72 2.2 POWER CONSIDERATIONS The average chip-junction temperature, T , in deJ grees Celsius, may be calculated using the following equation: TJ = TA + (PD x JA) (1) Therefore: Where: - TA is the Ambient Temperature inC, - JA is the Package Junction-to-Ambient Thermal Resistance, in C/W, - PD is the sum of PINT and PI/O, - PINT is the product of IDD and VDD, expressed in Watts. This is the Chip Internal Power - PI/O represents the Power Dissipation on Input and Output Pins; User Determined. For most applications PI/O An approximate relationship between P and TJ D (if PI/O is neglected) is given by: PD = K/ (TJ + 273C) (2) K = PD x (TA + 273C) + JA x PD2 (3) Where: - K is a constant for the particular part, which may be determined from equation (3) by measuring PD (at equilibrium) for a known T Using this valA. ue of K, the values of PD and TJ may be obtained by solving equations (1) and (2) iteratively for any value of TA. JA 112/119 110 ST72E72 - ST72T72 2.3 DC ELECTRICAL CHARACTERISTICS (TA = 0 to +70C unless otherwise specified Symbol VDD V OL V OL V OL V OL V OL VOH VIH VIL Parameter Supply Voltage Output Voltage Low Port A (Open drain) Output Voltage Low Port B (0-7), Port D(0:7) Push-pull Output Voltage Low Port C (PC2,PC3,PC4) Push-pull Output Voltage Low Port C (PC0,PC1,PC5) Open drain during Power ON Reset and Watchdog Reset Output Voltage High Push-pull Input High Voltage PA(0-7), PB(0-7), PC(0-5), PD(0-4), RESET Input Low Voltage PA(0-7), PB(0-7), PC(0-5), PD(0-4), RESET I/O Ports Hi-Z Leakage Current PA(0-7), PB(0-7), PC(0-5), PD(0-4), RESET COUT CIN RON IRPU Capacitance: Ports (as Input or Output), RESET DA1,D(A3-17)(PWM/BRM) Serial Resistor Pull-up resistor current VDD=5v VIN=VSS 700 20 IOH =1.6 mA Leading Edge Trailing Edge VSS 10 VDD 12 8 1000 uA pF pF Ohms uA VDD-0.8 0.7xV DD V SS VDD 0.3xV DD IOL=1.6 mA Test Condit ions Value min 4.5 typ max 5.5 0.4 Unit V V V V V V V V V uA IOL=1.6 mA IOL=1.6 mA IOL=1.6 mA 0.4 0.4 0.4 0.4 IIL 113/119 111 ST72E72 - ST72T72 DC ELECTRICAL CHARACTERISTICS(Cont'd) DDC Bus (I2C INTERFACE) Symbol Parameter Hysteress of Shmitt trigger inputs VHYS TSP TOF fixed input levels VDD-related input levels Pulse width of spikes which must be suppressed by the input filter Output fall time from VIHmin to VILmax with a bus capacitance from 10 pF to 400pF with up 3mA sink current at VOL1 I C Input current each I/O pin with an input voltage between 0.4v and 0.9 VDD max Capacitive load for each I/O pin -10 250 10 10 A pF ns na na na na na na ns V Min Max Unit A/D CONVERTER Symbol Val Terr Tcon Rva Parameter Resolution Total Error Conversion Time Analog Source Impedance Test Conditions FOSC = 8 MHz FOSC = 8 MHz FOSC = 8 MHz 16 30 Min Typ 8 3 Max Unit bit LSB s K 114/119 112 ST72E72 - ST72T72 2.4 AC ELECTRICAL CHARACTERISTICS (TA = 0 to +70C unless otherwise specified) Symbol V DD Parameter Operating Supply Voltage Test Condition s 4 MHz Internal RUN Mode Fext = 8MHz IDD Supply Current VDD = 5.0V WAIT Mode fext = 8MHz VDD = 5.5V 3.5 5 mA Value Min 4.5 7.5 Typ. Max 5.5 10 Unit V mA 2.5 CONTROL TIMING (Operating conditions TA 0 to +70C unless otherwise specified) Symbol fOSC tILCH tRL tPORL TDOGL tDOG tILIL tOXOV tDDR Parameter Frequency of Operation Halt Mode Recovery Startup Time External RESET Input pulse Width Power Reset Duration Watchdog RESET Output Pulse Width Watchdog Time-out Interrupt Pulse Period Crystal Oscillator Start-up Time Power up rise time VDD min 1.5 4096 2 49,152 (1) 50 100 2 3,145,728 Test Condition s VDD = 4.5V f external f internal Value Min Typ. Max 8 4 20 Unit MHz ms tCYC tCYC tCYC tCYC tCYC ms ms Notes : 1. The minimum period tILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 cycles. 115/119 113 ST72E72 - ST72T72 AC ELECTRICAL CHARACTERISTICS(Cont'd) 2.5.1 DDC (I2C BUS) INTERFACE 2.5.1.1 Timing Parameter Bus free time between a STOP and START condition Hold time START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Capacitive load for each bus line 4.0 400 Min 4.7 4.0 4.7 4.0 4.7 250 (1) 250 1000 300 Max Symbol Tubs Thd:sta Tlow Thigh Tsu:sta Thd:dat Tsu:dat Tr Tf Tsu:sto Cb Unit ms s s s s ns ns ns ns ns pF 1. The device provides a hold time of at least 250ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. Cb = total capacitance of one bus line in pF Figure 2. Definition of Timing Terminology SDA Tbuf SCL Tlow Tr Tf Thd:sta Tsp Thd:sta Thd:dat Thigh Tsu:dat Tsu:sta Tsu:sto 116/119 114 ST72E72 - ST72T72 3 GENERAL INFORMATION 3.1 PACKAGE MECHANICAL DATA Figure 3. 56 Shrink Plastic Dual In Line Package, 600-mil Width Dim A A1 B B1 C D D1 E E1 K1 K2 L e1 2.54 1.78 13.72 0.070 0.51 0.35 0.75 0.20 52.12 18.54 mm Min Typ Max 5.08 0.020 0.59 0.014 1.42 0.030 0.36 0.008 2.052 0.730 0.540 0.150 0.023 0.056 0.014 Min inches Typ Max 0.200 3.81 0.100 Number of Pins N 56 3.2 ORDERING INFORMATION Sales Types ST 72E72N5D1 ST 72T72N5B1 EPROM/OTP Size 24K 24K RAM Size 384 384 Temperature Range 25C 0 to +70C Package CSDIP56 PSDIP56 117/119 115 ST7272 ST72T72 MICROCONTROLLER OPTION LIST Customer Address . .. ... . . .. . . .. .. .. . . .. . .. . .. . ... .. . . .. . ... . .. . . . ... . . .. . . .. . .. .. . . .. ... . . .. . . .. .. .. . . .. . .. . .. . ... .. . . .. . ... . .. . . . ... . . .. . . .. . .. .. . . .. . . . ... . .. ... . . .. .. . . .. . .. . .. . .. .. . . .. . .. . . ... . .. ... ... .. .. . .. . Contact Phone No . .. ... . . .. . . .. .. .. . . .. . .. . .. . ... .. . . .. . ... . .. . . . ... . . .. . . .. . .. .. . . .. ... . . .. . . .. .. .. . . .. . .. . .. . ... .. . . .. . ... . .. . . . ... . . .. . . .. . .. .. . Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SGS-THOMSON Microelectronics references Device: [ ] ST72T72N5B1 24K OTP CLPOUT OPTION: Maximum delay 250ns Programmable back porch clamping width (0, 250ns, 500ns, 1 us) Package: PSDIP56 [ ] ST72E72N5B1 24K EPROM CLPOUT OPTION: Maximum delay 250ns Programmable back porch clamping width (0, 250ns, 500ns, 1 us) Package: CSDIP56 [ ] ST72T72M5B1 24K OTP CLPOUT OPTION: Maximum delay 125ns Programmable back porch clamping width (0, 125ns, 250ns, 500 us) Package: PSDIP56 [ ] ST72E72M5B1 24K EPROM CLPOUT OPTION: Maximum delay 125ns Programmable back porch clamping width (0, 125ns, 250ns, 500 us) Package: CSDIP56 Temperature Range: [ ] 0C to + 70C Signature Date 118/119 ST7272 Notes: Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMS ON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c)1996 SGS-THOMS ON Microelectronics -Printed in Italy - All Rights Reserved. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 119/119 |
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